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參數(shù)資料
型號(hào): MAX9939AUB+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 14/15頁(yè)
文件大小: 0K
描述: IC AMP PGA SPI VOS I/O 10MSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
放大器類(lèi)型: 可編程增益
電路數(shù): 2
輸出類(lèi)型: 差分
轉(zhuǎn)換速率: 9 V/µs
增益帶寬積: 2.15MHz
電流 - 輸入偏壓: 1pA
電壓 - 輸入偏移: 1500µV
電流 - 電源: 3.4mA
電流 - 輸出 / 通道: 70mA
電壓 - 電源,單路/雙路(±): 2.9 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
MAX9939
SPI Programmable-Gain Amplifier
with Input VOS Trim and Output Op Amp
8
Maxim Integrated
CMRR, gain accuracy, and very low temperature drift
due to precise resistor matching. The output of this
amplifier is level shifted to VCC/2.
This amplifier is followed by a programmable-gain
inverting amplifier (amplifier A) with programmable RF
and RI resistors whose gain varies between 0.2V/V and
157V/V. The output of this amplifier is biased at
VCC/2 and has extremely high gain accuracy and low
temperature drift.
The MAX9939 has an uncommitted op amp (amplifier
B) whose noninverting input is referenced to VCC/2. Its
inverting input and output are externally accessible,
allowing it to be configured either as an active filter or
as a differential output.
A robust input ESD protection scheme allows input volt-
ages at INA+ and INA- to reach ±16V without damag-
ing the MAX9939, thus making the part extremely
attractive for use in front-ends that can be exposed to
high voltages during fault conditions. In addition, its
input-voltage range extends down to -VCC/2 (e.g., -2.5V
when powered from a 5V single supply) allowing the
MAX9939 to translate below ground signals to a 0V to
5V output signal. This feature simplifies interfacing
ground-referenced signals with unipolar-input ADCs.
SPI-Compatible Serial Interface
The MAX9939 has a write-only interface, consisting of
three inputs: the clock signal (SCLK), data input (DIN),
and chip-select input (CS). The serial interface works
with the clock polarity (CPOL) and clock phase (CPHA)
both set to 0 (see Figure 1). Initiating a write to the
MAX9939 is accomplished by pulling CS low. Data is
clocked in on the rising edge of each clock pulse, and
is written LSB first. Each write to the MAX9939 consists
of 8 bits (1 byte). Pull CS high after the 8th bit has been
clocked in to latch the data and before sending the
next byte of instruction. Note that the internal register is
not updated if CS is pulled high before the falling edge
of the 8th clock pulse.
Register Description
The MAX9939 consists of three registers: a shift register
and two internal registers. The shift register accepts
data and transfers it to either of the two internal regis-
ters. The two internal registers store data that is used to
determine the gain, input offset voltage, and operating
modes of the amplifier. The two internal registers are the
Input VOS Trim register and Gain register. The format of
the 8-bit write to these registers is shown in Tables 1
and 2. Data is sent to the shift register LSB first.
SEL: The SEL bit selects which internal register is writ-
ten to. Set SEL to 0 to write bits D5:D1 to the input VOS
trim register. Set SEL to 1 to write D4:D1 to the Gain
register (D5 is don’t care when SEL = 1).
CS
SCLK
DIN
D0
D1
D2
D3
D6
D5
D6
D7
Figure 2. SPI Interface Timing Diagram (CPOL = CPHA = 0)
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
SHDN MEAS
V4
V3
V2
V1
V0
SEL = 0
Table 1. Input VOS Trim Register
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
SHDN MEAS
X
G3
G2
G1
G0
SEL = 1
X = Don’t care.
Table 2. Gain Register
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