參數(shù)資料
型號(hào): MAXQ61CA-XXXX+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, QCC32
封裝: ROHS COMPLAINT, TQFN-32
文件頁(yè)數(shù): 2/26頁(yè)
文件大小: 1372K
代理商: MAXQ61CA-XXXX+
16-Bit Microcontroller with Infrared Module
MAXQ61C
10 _____________________________________________________________________________________
Pin Description (continued)
PIN
NAME
FUNCTION
BARE DIE
32 TQFN-
EP
44 TQFN-
EP
Port 2 General-Purpose, Digital I/O Pins. These port pins function as
general-purpose I/O pins with their input and output states controlled by
the PD2, PO2, and PI2 registers. All port pins default to high-impedance
mode after a reset. Software must configure these pins after release
from reset to remove the high-impedance condition. All special func-
tions must be enabled from software before they can be used.
GPIO PORT PIN
SPECIAL FUNCTION
9
8
P2.0/MOSI
P2.0
SPI: Master Out-Slave In
10
9
P2.1/MISO
P2.1
SPI: Master In-Slave Out
11
10
P2.2/SCLK
P2.2
SPI: Slave Clock
12
11
P2.3/SSEL
P2.3
SPI: Active-Low Slave Select
28
18
29
P2.4/TCK
P2.4
JTAG: Test Clock
29
19
30
P2.5/TDI
P2.5
JTAG: Test Data In
30
20
31
P2.6/TMS
P2.6
JTAG: Test Mode Select
31
21
32
P2.7/TDO
P2.7
JTAG: Test Data Out
Port 3 General-Purpose, Digital I/O Pins with Interrupt Capability. These
port pins function as general-purpose I/O pins with their input and out-
put states controlled by the PD3, PO3, and PI3 registers. All port pins
default to high-impedance mode after a reset. Software must configure
these pins after release from reset to remove the high-impedance con-
dition. All external interrupts must be enabled from software before they
can be used.
GPIO PORT PIN
EXTERNAL INTERRUPT
19
18
P3.0/INT8
P3.0
INT8
20
19
P3.1/INT9
P3.1
INT9
21
20
P3.2/INT10
P3.2
INT10
22
21
P3.3/INT11
P3.3
INT11
23
22
P3.4/INT12
P3.4
INT12
24
23
P3.5/INT13
P3.5
INT13
25
24
P3.6/INT14
P3.6
INT14
26
25
P3.7/INT15
P3.7
INT15
NO CONNECTION PINS
15, 16
26, 27
N.C.
No Connection. Not internally connected.
EP
Exposed Pad. For low-current applications (< 10mA of GPIO current,
exclusive of IRTX sink current), these pins can be left unconnected. If
used, they should be connected directly to the ground plane.
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