參數(shù)資料
型號(hào)： MB15F83ULPVA
廠商： FUJITSU LTD
元件分類： XO, clock
英文描述： Fractional-N PLL Frequency Synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 2000 MHz, PBCC20
封裝： PLASTIC, BCC-20
文件頁(yè)數(shù)： 8/29頁(yè)
文件大?。?/td> 168K
代理商： MB15F83ULPVA
MB15F83UL
8
I
FUNCTIONAL DESCRIPTION
1.
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections and programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary code is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
Note
:
(CN3
=
1 is pohibited)
(1) Serial data format
LSB
The programmable
reference counter for
the IF-PLL
The programmable
counter and the
swallow counter for the
IF-PLL
The programmable
reference counter for
the RF-PLL
The prgrammable
counter and the
swallow counter for
the RF-PLL
CN1
0
1
0
1
CN2
0
0
1
1
CN3
0
0
0
0
Note: Data input with MSB first.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
0
0
R
C1
R
C2
R
C3
R
C4
R
C5
R
C6
R
C7
R
C8
R
C9
R
C10
R
C11
R
C12
R
C13
R
C14
LDS
T1
T2 SW
C
FC
C
CS
C
1
0
0
A
C1
A
C2
A
C3
A
C4
0
0
0
N
C1
N
C2
N
C3
N
C4
N
C5
N
C6
N
C7
N
C8
N
C9
N
C10
N
C11
X
X
0
1
0
R
F1
R
F2
R
F3
R
F4
R
F5
R
F6
R
F7
0
0
0
0
0
0
0
0
SC1 SC2
1
FC
F
CS
F
1
1
0
A
F1
A
F2
A
F3
A
F4
0
N
F1
N
F2
N
F3
N
F4
N
F5
N
F6
N
F7
N
F8
N
F9
N
F10
F1
F2
F3
F4
0
R
C1
to R
C14
A
C1
to A
C4
N
C1
to N
C11
LDS, T1, T2
SW
C
FC
C
CS
C
R
F1
to R
F7
A
F1
to A
F4
N
F1
to N
F10
F1 to F4
SC1, SC2
FC
F
CS
F
X
: Divide ratio setting bits for the reference counter of the IF (3 to 16383)
: Divide ratio setting bits for the swallow counter of the IF (0 to 15, A < N)
: Divide ratio setting bits for the programmable counter of the IF (3 to 2047)
: Select bits for the lock detect output or a monitoring phase comparison frequency
: Divide ratio setting for the prescaler of the IF
: Phase control bit for the phase detector of the IF
: Charge pump current select bit of the IF
: Divide ratio setting bits for the reference counter of the RF (3 to 127)
: Divide ratio setting bits for the swallow counter of the RF (0 to 15, A < N
2)
: Divide ratio setting bits for the programmable counter of the RF (18 to 1023)
: Fractional-N increment setting bit for the fractional accumulator (0 to 15, F < Q)
: Spurious cancel set bit of the RF.
: Phase control bit for the phase detector of the RF.
: Charge pump current select bit of the RF
: Dummy bit (Set “0” or “1”)
MSB
Direction of data shift
Control bit (CN3)
Control bit (CN2)
Control bit (CN1)
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