參數(shù)資料
型號： MB15F88ULPFT
廠商： FUJITSU LTD
元件分類： XO, clock
英文描述： Fractional-N PLL Frequency Synthesizer
中文描述： PLL FREQUENCY SYNTHESIZER, 2600 MHz, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁數(shù)： 3/29頁
文件大小： 175K
代理商： MB15F88ULPFT
MB15F88UL
3
I
PIN DESCRIPTION
Pin no.
Pin
name
I/O
Descriptions
TSSOP BCC
1
19
OSC
IN
I
The programmable reference divider input pin. TCXO should be connected with an
AC coupling capacitor.
Ground pin for OSC input buffer and the shift register circuit.
Prescaler input pin for the TX-PLL.
Connection to an external VCO should be AC coupling.
2
20
GND
3
1
fin
TX
I
4
2
Xfin
TX
I
Prescaler complimentary input pin for the TX-PLL section.
This pin should be grounded via a capacitor.
Ground pin for the TX-PLL section.
Power supply voltage input pin for the TX-PLL section (except for the charge pump
circuit) , the shift register and the oscillator input buffer.
When power is OFF, latched data of TX-PLL is lost.
5
3
GND
TX
6
4
V
CCTX
7
5
PS
TX
I
Power saving mode control pin for the TX-PLL section. This pin must be set at “L”
when the power supply is started up. (Open is prohibited.)
PS
TX
=
“H” ; Normal mode, PS
TX
=
“L” ; Power saving mode
Power supply voltage input pin for the TX-PLL charge pump.
Charge pump output pin for the TX-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
8
6
Vp
TX
9
7
Do
TX
O
10
8
LD/fout O
Look detect signal output (LD) /phase comparator monitoring output (fout) pins.
The output signal is selected by an LDS bit in a serial data.
LDS bit
=
“H” ; outputs fout signal, LDS bit
=
“L” ; outputs LD signal
Charge pump output pin for the RX-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
Power supply voltage input pin for the RX-PLL charge pump.
Power saving mode control pin for the RX-PLL section. This pin must be set at “L”
when the power supply is started up. (Open is prohibited. )
PS
RX
=
“H” ; Normal mode, PS
RX
=
“L” ; Power saving mode
Power supply voltage input pin for the RX-PLL section (except for the charge pump
circuit) .
Ground pin for the RX-PLL section.
Prescaler complimentary input pin for the RX-PLL section.
This pin should be grounded via a capacitor.
11
9
Do
RX
O
12
10
Vp
RX
13
11
PS
RX
I
14
12
V
CCRX
15
13
GND
RX
16
14
Xfin
RX
I
17
15
fin
RX
I
Prescaler input pin for the RX-PLL.
Connection to an external VCO should be AC coupling.
18
16
LE
I
Load enable signal input pin (with the schmitt trigger circuit.)
On a rising edge of load enable, data in the shift register is transferred to the cor-
responding latch according to the control bit in a serial data.
19
17
Data
I
Serial data input pin (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (TX-ref counter, TX-prog. counter,
RX-ref. counter, RX-prog. counter) according to the control bit in a serial data.
20
18
Clock
I
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the clock.
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