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參數(shù)資料
| 型號： | MB15G000 |
| 廠商： | Fujitsu Limited |
| 英文描述： | ASTRO-NT (for RF front-end LSI-Based on PLL, Analog Macro) |
| 中文描述： | 天文學新臺幣（射頻前端大規(guī)模集成電路，鎖相環(huán)，模擬基于宏） |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 296K |
| 代理商： | MB15G000 |
MB15G000 Series
4
I
MACRO DESCRIPTIONS
1.
Prescaler
Divides the reference frequency by any given value and outputs the resulting frequency. Choice of two -modulus
or fixed output mode.
PLL
Phase comparator
The phase comparator has a phase detection range of –2
π
to +2
π
, and is designed to eliminate blind spots in
phase comparison by output of a margin-of-error signal to the charge pump even when the phase difference is
zero. Phase comparator characteristics can also be tuned to the polarity of VCO.
Counters
2.
The divide ratios of the comparator-side counter and reference-side counter can be either programmable or fixed.
Charge pump
The “H” level output voltage from the charge pump is determined by power supply voltage. Charge pump
characteristics for the sending and receiving systems can be optimized for each specific application.
For example, when FM modulation is applied directly to the VCO signal, charge pump characteristic can be
adjusted for lower speeds in order to reduce the sensitivity of the synthesizer loop so that output does not track
the modulation.
High speed lock-up circuit
This circuit is specially designed for faster lock-up speeds.
Intermittent operation control circuit
This on-chip power-saving function reduces circuit current flow in standby status, enabling devices to operate
with less power demand. A special circuit is built in to prevent excessive error signal from increasing lock-up
delay during the transition from power-saving mode to operating mode.
List of standard macros
Crystal oscillator input frequency: Up to 32 MHz
Standby mode current demand: 10
μ
A(Max.)
Note: Refer to macro specification book.
Type
V
CC
I
CC
Operating
frequency
Prescaler
divide ratio
(M)
Comparator
counter divide
ratio (N)
Swallow
counter
divide ratio
(A)
Reference
counter
divide ratio
(R)
PLL1
2.7 V
1.5 mA
0.5 GHz
8/9, 16/17
5 to 2047
0 to 255
5 to 16383
PLL2
2.0 mA
1.2 GHz
32/33, 64/65
PLL3
3.0 mA
2.0 GHz
PLL4
3.5 mA
2.5 GHz
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