參數(shù)資料
型號: MB15S00
廠商: Fujitsu Limited
英文描述: IF Band Phase Locked Loop (PLL) Frequency Synthesizer(中頻鎖相環(huán)頻率合成器)
中文描述: 中頻帶鎖相環(huán)路(PLL)頻率合成器(中頻鎖相環(huán)頻率合成器)
文件頁數(shù): 6/18頁
文件大?。?/td> 123K
代理商: MB15S00
6
MB15S00 Series
I
FUNCTIONAL DESCRIPTIONS
Divide ratios of the internal counters can be set optionally according to customer requirements. Two different frequencies
can be selected by Div input ”H” or ”L”.
The divide ratio can be calculated using the following equation:
÷
R (A < N)
f
VCO
= {(P x N) + A} x f
OSC
f
P:
N:
A:
f
OSC
R:
VCO
:
Output frequency of external voltage controlled ocillator (VCO: up to 300MHz)
Preset divide ratio of dual modulus prescaler (16/17 or 32/33)
Divide ratio of the main counter (5 to 4,095)
Divide ratio of the swallow counter (0 to
Reference oscillation frequency ( up to 23MHz)
Divide ratio of the reference counter (5 to 4,095)
31)
:
I
PHASE DETECTOR TIME CHART
Note:
(e.g. tW635ns to 1250ns when foscin = 12.8 MHz)
Phase defference detection range = –2
Spikes on Do pulse during locking state are output to prevent dead zone.
LD output becomes low when phase difference is tw or more.
LD output becomes high when phase difference is tw or less and continues to be so for three cycles or more.
tw depends on OSCin input frequency.
π
to + 2
π
t
W
fr
fp
t
W
LD
D
O
Z
L
H
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