參數(shù)資料
型號(hào): MB40568P-SK
廠商: FUJITSU LTD
元件分類: ADC
英文描述: A/D Converter (1-channel, 8-bit low-power model with built-in clamp circuit)
中文描述: 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP22
封裝: SKINNY, PLASTIC, DIP-22
文件頁數(shù): 6/24頁
文件大?。?/td> 175K
代理商: MB40568P-SK
6
MB40568
I
ABSOLUTE MAXIMUM RATINGS (See WARNING)
* :Package : SOP
V
CCA
= 2.0 ± 0.1 V, V
RB
= 2.0 ± 0.1 V
WARNING:
Permanent device damage may occur if the above
Absolute Maximum Ratings
are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
I
RECOMMENDED OPERATING CONDITIONS
*1: V
CCA
and V
CCD
must be used in the same voltage level.
*2: Package : SOP
V
CCA
= 2.0 ± 0.1 V, V
RB
= 2.0 ± 0.1 V
*3: V
INC
must have an amplitude of V
CCA
– V
CLMP
.
Parameter
Symbol
Rating
Unit
Power supply voltage
V
CCA
, V
CCD
–0.5 to +7.0
V
Digital input voltage
V
IND
–0.5 to +7.0
V
Analog input voltage
V
INA
–0.5 to V
CC
+ 0.5
V
Analog reference voltage*
V
RB
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
V
Clamp circuit input voltage
V
INC
V
°
C
Storage temperature
Tstg
–55 to +125
Parameter
Symbol
Value
Unit
Min.
Typ.
Max.
Power supply voltage*
1
V
CCA
, V
CCD
4.75
5.00
5.25
V
Analog input voltage
V
INA
V
RB
V
CCA
V
Analog reference voltage*
2
V
RB
2.75
3
3.25
V
Clamp circuit input voltage*
3
V
INC
0
3
V
μ
F
μ
A
mA
Clamp capacitance
C
CLMP
1
Digital high-level output voltage
I
OH
–400
Digital low-level output voltage
I
OL
1.6
Clock pulse width at high-level
t
W+
22.5
ns
Clock pulse width at low-level
t
W–
22.5
ns
°
C
Operating temperature
Top
0
70
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