參數(shù)資料
型號: MB81116822A-67
廠商: Fujitsu Limited
英文描述: CMOS 2×1M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2×1M ×8位超級頁面存取模式動態(tài)RAM)
中文描述: 的CMOS 2 × 100萬× 8位超頁模式動態(tài)RAM(2 × 100萬的CMOS × 8位超級頁面存取模式動態(tài)內(nèi)存)
文件頁數(shù): 33/43頁
文件大?。?/td> 276K
代理商: MB81116822A-67
33
MB81116822A-125/-100/-84/-67
TIMING DIAGRAM – 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4)
Q1
Q2
(No change)
Q3
(No change)
Q4
D1
Not Written
D2
Not Written
D3
D4
CLK
CKE
CLK
(Internal)
DQ
(Read)
DQ
(Write)
Notes:
1.
The latency of CKE (l
CKE
) is one clock.
During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output
remain the same data.
During the write mode, data at the next clock of CSUS command is ignored.
2.
3.
3
3
2
2
2
2
I
CKE
(1 clock)
I
CKE
(1 clock)
1
1
TIMING DIAGRAM – 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT
NOP
PD(NOP)
Don’t Care
NOP
ACTV
CLK
CKE
Command
1 clock
(min)
1
2
3
NOP
3
Notes:
1.
Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.
Precharge command can be posted in conjunction with CKE when burst mode is ended at this clock.
The ACTV command can be latched after t
PDE
(min) + 1 clock (min). It is recommended to apply NOP command in conjunction
with CKE. It is also recommended to apply minimum of 4 clocks to stabilize external clock prior to ACTV command.
2.
3.
t
PDE
t
PEF
(max)
相關PDF資料
PDF描述
MB81116822A-84 CMOS 2×1M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2×1M ×8位超級頁面存取模式動態(tài)RAM)
MB811171622A-100 CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動態(tài)RAM)
MB811171622A-125 CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動態(tài)RAM)
MB811171622A-67 CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動態(tài)RAM)
MB811171622A-84 CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動態(tài)RAM)
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