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參數(shù)資料
| 型號： | MB811171622A-67 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動態(tài)RAM) |
| 中文描述： | 的CMOS為512k × 2 × 16位同步動態(tài)隨機存儲器（2 ×的CMOS為512k × 16位同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 1/43頁 |
| 文件大?。?/td> | 601K |
| 代理商： | MB811171622A-67 |
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1
DS05-11024-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
2
×
512 K
SYNCHRONOUS DYNAMIC RAM
MB811171622A-125/-100/-84/-67
×
16 BITS
CMOS 2-BANK 524,288-WORD
Synchronous Dynamic Random Access Memory
×
16 BITS
I
DESCRIPTION
The Fujitsu MB811171622A is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
16,777,216 memory cells accessible in an 16-bit format. The MB811171622A features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB811171622A SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a standard DRAM.
The MB811171622A is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
I
PRODUCT LINE & FEATURES
Parameter
MB811171622A
-100
100 MHz max.
10 ns min.
54 ns max.
24 ns max.
8.5 ns max.
130 mA max.
2 mA max.
-125
-84
-67
Clock Frequency
Burst Mode Cycle Time
RAS Access Time
CAS Access Time
Access Time From Clock (CL = 3)
Operating Current (Two banks active)
Power Down Mode Current
125 MHz max.
8 ns min.
45 ns max.
21 ns max.
7.5 ns max.
140 mA max.
84 MHz max.
12 ns min.
56 ns max.
26 ns max.
8.5 ns max.
120 mA max.
67 MHz max.
15 ns min.
60 ns max.
30 ns max.
9 ns max.
110 mA max.
Single +3.3 V Supply +0.3 V tolerance
LVTTL compatible I/O
2 K refresh cycles every 32.8 ms
Dual bank operation
Byte control by DQML/DQMU
Burst read/write operation and burst read/
single write operation capability
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
Programmable burst type, burst length, and
CAS latency
Auto-and Self-refresh (every 16
μ
s)
CKE power down mode
Output Enable and Input Data Mask
相關(guān)PDF資料 |
PDF描述 |
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| MB811171622A-84 | CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動態(tài)RAM) |
| MB81117422A-100 | CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動態(tài)RAM) |
| MB81117422A-125 | CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動態(tài)RAM) |
| MB81117422A-67 | CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動態(tài)RAM) |
| MB81117422A-84 | CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動態(tài)RAM) |
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