參數(shù)資料
型號： MB81116822A-84
廠商： Fujitsu Limited
英文描述： CMOS 2×1M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2×1M ×8位超級頁面存取模式動態(tài)RAM)
中文描述： 的CMOS 2 × 100萬× 8位超頁模式動態(tài)RAM（2 × 100萬的CMOS × 8位超級頁面存取模式動態(tài)內(nèi)存）
文件頁數(shù)： 19/43頁
文件大小： 276K
代理商： MB81116822A-84
19
MB81116822A-125/-100/-84/-67
DATA INPUT AND OUTPUT (DQ
0
to DQ
7
)
Input data is latched and written into the memory at the clock following the Write command input. Data output
is obtained by the following conditions followed by a Read command input:
t
RAC
: from the Bank Active command when t
RCD
(min) is satisfied. (This parameter is reference only.)
t
CAC
: from the Read command when t
RCD
is greater than t
RCD
(min).
t
AC
: from the clock edge after t
RAC
and t
CAC
.
The polarity of the output data is identical to that of the input. Data is valid between access time (determined
by the three conditions above) and the next positive clock edge (t
OH
).
DATA I/O MASK (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and
when DQM = High is latched by a clock, input is masked at the same clock and output will be masked at the
second clock later while internal burst counter will increment by one or will go to the next stage depending on
burst type.
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row
address and by automatic strobing column address. Access time and cycle time of Burst mode is specified as
t
AC
and t
CK
, respectively. The internal column address counter operation is determined by a mode register which
defines burst type and burst count length of 1,2 or 4 bits of boundary. In order to terminate or to move from the
current burst mode to the next stage while the remaining burst count is more than 1, the following combinations
will be required:
The burst type can be selected either sequential or interleave mode if burst length is 2 or 4. The sequential
mode is an incremental decoding scheme within a bundary address to be determined by count length, it
assigns+1 to the previous (or initial) address until reaching the end of boundary address and then wraps round
to least significant address(= 0). The interleave mode is a scrambled decoding scheme for A
0
and A
2
. If the first
access of column address is even (0), the next address will be odd (1), or vice-versa.
Current Stage
Next Stage
Method (Assert the following command)
Burst Read
Burst Read
Read Command
Burst Read
Burst Write
1st Step
Mask Command (Normally 3 clock cycles)
2nd Step
Write Command after l
OWD
Burst Write
Burst Write
Write Command
Burst Write
Burst Read
Read Command
Burst Read
Precharge
Precharge Command
Burst Write
Precharge
Precharge Command
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