參數(shù)資料
型號： MB811171622A-100
廠商： Fujitsu Limited
英文描述： CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動(dòng)態(tài)RAM)
中文描述： 的CMOS為512k × 2 × 16位同步動(dòng)態(tài)隨機(jī)存儲器（2 ×的CMOS為512k × 16位同步動(dòng)態(tài)RAM）的
文件頁數(shù)： 19/43頁
文件大?。?/td> 601K
代理商： MB811171622A-100
19
MB811171622A-125/-100/-84/-67
DATA INPUT AND OUTPUT (DQ
0
to DQ
15
)
Input data is latched and written into memory at the clock following the write command input. Data output is obtained
by the following conditions followed by a read command input:
t
RAC
; from the bank active command when t
RCD
(min) is satisfied. (This parameter is reference only.)
t
CAC
; from the read command when t
RCD
is greater than t
RCD
(min).
t
AC
; from the clock edge after t
RAC
and t
CAC
.
The polarity of the output data is identical to that of the input. Data is valid between access time (determined by
the three conditions above) and the next positive clock edge (t
OH
).
DATA I/O MASK (DQML/DQMU)
DQML and DQMU are active high enable inputs and have an output disable and input mask function. During burst
cycle and when DQML/DQMU = High is latched by a clock, input is masked at the same clock and output will be
masked at the second clock later while internal burst counter will increment by one or will go to the next stage
depending on burst type.
DQML controls lower byte (DQ
0
to DQ
7
) and DQMU (DQ
8
to DQ
15
) controls upper byte.
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address
and by automatic strobing column address. Access time and cycle time of Burst mode is specified as t
AC
and t
CK
,
respectively. The internal column address counter operation is determined by a mode register which defines burst
type and burst count length of 1,2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst
mode to the next stage while the remaining burst count is more than 1, the following combinations will be required:
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode
is an incremental decoding scheme within a boundary address to be determined by count length, it assigns+1 to
the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant
address(= 0). The interleave mode is a scrambled decoding scheme for A
0
and A
2
. If the first access of column
address is even (0), the next address will be odd (1), or vice-versa.
Current Stage
Next Stage
Method (Assert the following command)
Burst Read
Burst Read
Read Command
Burst Read
Burst Write
1st Step
Mask Command (Normally 3 clock cycles)
2nd Step
Write Command after l
OWD
Burst Write
Burst Write
Write Command
Burst Write
Burst Read
Read Command
Burst Read
Precharge
Precharge Command
Burst Write
Precharge
Precharge Command
相關(guān)PDF資料
PDF描述
MB811171622A-125 CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動(dòng)態(tài)RAM)
MB811171622A-67 CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動(dòng)態(tài)RAM)
MB811171622A-84 CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動(dòng)態(tài)RAM)
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MB81117422A-125 CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動(dòng)態(tài)RAM)
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