參數(shù)資料
型號(hào)： MB811171622A-125
廠商： Fujitsu Limited
英文描述： CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動(dòng)態(tài)RAM)
中文描述： 的CMOS為512k × 2 × 16位同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（2 ×的CMOS為512k × 16位同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 14/43頁(yè)
文件大?。?/td> 601K
代理商： MB811171622A-125
14
MB811171622A-125/-100/-84/-67
(Continued)
Notes:
1. All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle.
2. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state
of that bank.
3. Illegal if any bank is not idle.
4. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
5. NOP to bank precharging or in idle state.
May precharge bank spesified by BA (and AP).
6. SELF command should only be issued after the last read data have been appeared on DQ.
7. MRS command should only be issued on condition that all DQ are in Hi-Z.
Current
State
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Addr
Function
Notes
Bank Active
Bank
Activating
Read/Write
H
H
X
X
X
X
X
Refer to the Operation Command Table.
H
L
X
X
X
X
X
Begin Clock Suspend Next Cycle
L
H
X
X
X
X
X
Exit Clock Suspend Next Cycle
L
L
X
X
X
X
X
Maintain Clock Suspend
Clock
Suspend
H
X
X
X
X
X
X
Invalid
L
H
X
X
X
X
X
Exit Clock Suspend Next Cycle
L
L
X
X
X
X
X
Maintain Clock Suspend
Any State
Other Than
Listed
Above
L
X
X
X
X
X
X
Invalid
H
H
X
X
X
X
X
Refer to the Operation Command Table.
H
L
X
X
X
X
X
Begin Clock Suspend Next Cycle
相關(guān)PDF資料
PDF描述
MB811171622A-67 CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動(dòng)態(tài)RAM)
MB811171622A-84 CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動(dòng)態(tài)RAM)
MB81117422A-100 CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動(dòng)態(tài)RAM)
MB81117422A-125 CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動(dòng)態(tài)RAM)
MB81117422A-67 CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動(dòng)態(tài)RAM)
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