參數(shù)資料
型號(hào)： MB811171622A-84
廠商： Fujitsu Limited
英文描述： CMOS 2×512K×16 Bit Synchronous Dynamic RAM(CMOS 2×512K×16 位同步動(dòng)態(tài)RAM)
中文描述： 的CMOS為512k × 2 × 16位同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（2 ×的CMOS為512k × 16位同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 28/43頁(yè)
文件大?。?/td> 601K
代理商： MB811171622A-84
28
MB811171622A-125/-100/-84/-67
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Notes:
*1.
I
CC
depends on the output termination or load conditions, clock cycle rate, and signal clocking rate and
address change; The specified values are obtained with the output open and no termination register
and one time address change.
An initial pause (DESL or NOP) of 200
μ
s is required after power-up followed by a minimum of eight
Auto-refresh cycles.
AC characteristics assume t
T
= 1 ns and 50 pF of capacitive load.
1.4 V is the reference level for measuring timing of input signals. Transition times are measured between
V
IH
(min) and V
IL
(max).
Maximum value of CL = 2 depends on t
CK
.
t
AC
also specifies the access time at burst mode except for first access.
Specified where output buffer is no longer driven. t
OH
, t
LZ
and t
HZ
define the time at which the output
level achieves
±
200 mV.
Actual clock count of t
RC
(l
RC
) will be sum of clock count of t
RAS
(l
RAS
) and t
RP
(l
RP
).
t
RAC
is a reference value. Maximum value is obtained from the sum of t
RCD
(min) and t
CAC
(max).
t
CAC
is a reference value.
Operation within the t
RCD
(min) ensures that t
RAC
can be met; if t
RCD
is greater than the specified
t
RCD
(min), access time is determined by t
CAC
or t
AC
.
All base values are measured from the clock edge at the command input to the clock edge for the next
command input. All clock counts are calculated by a simple formula: clock count equals base value
divided by clock period (round off to a whole number).
The t
CAC
depend on the CAS Latency.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
*10.
*11.
*12.
*13.
Parameter
Notes
Symbol
MB81116822A
-125
MB81116822A
-100
MB81116822A
-87
MB81116822A
-67
Unit
CKE to Clock Disable
l
CKE
1
1
1
1
cycle
DQM to Output in High-Z
l
DQZ
2
2
2
2
cycle
DQM to Input Data Delay
l
DQD
0
0
0
0
cycle
Last Output to Write Command
Delay
l
OWD
2
2
2
2
cycle
Write Command to Input Data
Delay
l
DWD
0
0
0
0
cycle
Precharge to Output
in High-Z Delay
CL = 2
l
ROH
2
2
2
2
cycle
CL = 3
3
3
3
3
cycle
Burst Stop Command
to Output in High-Z
Delay
CL = 2
l
BSH
2
2
2
2
cycle
CL = 3
3
3
3
3
cycle
Mode Register Access to Banks
Active
l
MRD
2
2
2
2
cycle
CAS to CAS Delay (min)
l
CCD
1
1
1
1
cycle
CAS Bank Delay (min)
l
CBD
1
1
1
1
cycle
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