參數(shù)資料
型號(hào): MB81117422A-84
廠商: Fujitsu Limited
英文描述: CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動(dòng)態(tài)RAM)
中文描述: 的CMOS 2 × 200萬(wàn)× 4位同步動(dòng)態(tài)RAM(2 × 200萬(wàn)的CMOS × 4位同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 15/44頁(yè)
文件大?。?/td> 273K
代理商: MB81117422A-84
15
MB81117422A-125/-100/-84/-67
(Continued)
Notes:
*1.
All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle.
Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the
state of that bank.
Illegal if any bank is not idle.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
NOP to bank precharging or in idle state. May precharge bank spesified by BA (and AP).
t
RRD
must be satisfied for other bank.
*2.
*3.
*4.
*5.
*6.
Current
State
CKE
n-1
CKE
n
CS
RAS CAS
WE
Addr
Function
Notes
Bank Active
Bank
Activating
Read/Write
H
H
X
X
X
X
X
Refer to the Operation Command Table
H
L
X
X
X
X
X
Begin Clock Suspend Next Cycle
L
H
X
X
X
X
X
Exit Clock Suspend Next Cycle
L
L
X
X
X
X
X
Maintain Clock Suspend
Clock
Suspend
H
X
X
X
X
X
X
Invalid
L
H
X
X
X
X
X
Exit Clock Suspend Next Cycle
L
L
X
X
X
X
X
Maintain Clock Suspend
Any State
Other Than
Listed Above
H
H
X
X
X
X
X
Refer to the Operation Command Table
H
L
X
X
X
X
X
Begin Clock Suspend Next Cycle
L
H
X
X
X
X
X
Exit Clock Suspend Next Cycle
L
L
X
X
X
X
X
Maintain Clock Suspend
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