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| 型號： | MB81117422A-84 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2×2M ×4 Bit Synchronous Dynamic RAM(CMOS 2×2M ×4 位同步動態(tài)RAM) |
| 中文描述： | 的CMOS 2 × 200萬× 4位同步動態(tài)RAM（2 × 200萬的CMOS × 4位同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 21/44頁 |
| 文件大小： | 273K |
| 代理商： | MB81117422A-84 |
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21
MB81117422A-125/-100/-84/-67
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations.
Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge
command (PRE). With the Precharge command, SDRAM will automatically be in standby state after precharge
time (t
RP
).
The precharged bank is selected by combination of AP and A
11
when Precharge command is asserted.
If AP = High, both banks are precharged regardless of A
11
(PALL). If AP = Low, a bank to be selected by A
11
is
precharged (PRE). The auto-precharge enters precharge mode at the end of burst mode of read or write without
Precharge command assertion. This auto precharge is entered by AP=High when a Read or Write command
is asserted. Refer to FUNCTION TRUTH TABLE.
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates
Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command.
The Auto-refresh command should also be asserted every 16
μ
s or a total 2048 refresh commands within a
32.8 ms period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue
the refresh function until cancelled by SELFX.
The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once
SDRAM enters the Self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or low level
state) and outputs will be in a High-Z state. During a Self-refresh mode, CKE = Low should be maintained. SELF
command should only be issued after last read data has been appeared on DQ.
SELF-REFRESH EXIT (SELFX)
To exit Self-refresh mode, apply minimum 4 clock cycles before CKE brought high, and then the NOP command
(NOP) or the Deselect command (DESL) should be asserted within one t
RC
period. CKE should be held High
within one t
RC
period after t
PDE
. Refer to Timing Diagram for the detail.
It is recommended to assert an Auto-refresh command just after the t
RC
period to avoid the violation of refresh
period.
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation
fields; Burst Length, Burst Type, CAS latency, and Operation Code. Refer to MODE REGISTER TABLE in page 32.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the
address line. Once a mode register is programmed, the contents of the register will be held until re-programmed
by another MRS command (or part loses power). MRS command should only be issued on condition that all
DQ is in Hi-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDRAM. Refer to POWER-UP INITIALIZATION below.
POWER-UP INITIALIZATION
The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On
Sequence to execute read or write operation.
1.
Apply power and start clock. Attempt to maintain either NOP or DESL command at the input.
2.
Maintain stable power, stable clock, and NOP condition for a minimum of 200
μ
s.
3.
Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
4.
Assert minimum of 8 Auto-refresh command(REF).
5.
Program the mode register by Mode Register Set command(MRS).
In addition, it is recommended DQM and CKE to track V
CC
to insure that output is High-Z state. The Mode Register
Set command (MRS) can be set before 8 Auto-refresh command (REF).
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