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參數(shù)資料
| 型號： | MB8116165B-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 1米× 16位的超頁模式動態(tài)RAM的CMOS（1米× 16位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 24/29頁 |
| 文件大?。?/td> | 575K |
| 代理商： | MB8116165B-60 |
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MB8116165B-50/-60
t
RC
HIGH-Z
t
RAS
t
RPC
t
CPN
t
CSR
t
CHR
t
RP
t
OFF
t
OH
t
CSR
t
CPN
t
RC
t
RP
t
ASR
t
RPC
HIGH-Z
t
RAH
t
OH
t
CRP
t
RAS
t
OFF
ROW ADDRESS
t
CRP
LCAS
or
UCAS
LCAS
or
UCAS
A
0
to A
11
V
IH
V
IL
V
OH
V
OL
RAS
V
IH
V
IL
V
IH
V
IL
DQ
(Output)
Fig. 16 – RAS-ONLY REFRESH (WE = OE = “H” or “L”)
DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 4,096 row
addresses every 65.6-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden
refresh.
RAS-only refresh is performed by keeping RAS Low and LCAS and UCAS High throughout the cycle; the row address to be
refreshed is latched on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state.
V
OH
V
OL
RAS
V
IH
V
IL
V
IH
V
IL
DQ
(Output)
Fig. 17 – CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = “H” or “L”)
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If LCAS or UCAS
is held Low for the specified setup time (t
CSR
) before RAS goes Low, the on-chip refresh control clock generators and refresh
address counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally
incremented in preparation for the next CAS-before-RAS refresh operation.
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB8116E | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:8116E |
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| MB8117800A-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM |
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