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參數(shù)資料
| 型號： | MB85342C-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 2M×32 BIT Hyper Page Mode DRAM Module(CMOS 2M×32位超級頁面存取模式動態(tài)RAM模塊) |
| 中文描述： | 的CMOS 200萬× 32位的超頁模式內(nèi)存的CMOS（200萬× 32位超級頁面存取模式動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 746K |
| 代理商： | MB85342C-60 |
8
MB85342C-60/-70
Notes:
*1.
An initial pause (RAS = CAS = V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-only
cycles or eight CAS-before-RAS refresh cycles (WE = V
IH
) before proper device operation is achieved.
If an internal refresh counter is used, a minimum of eight CAS-before-RAS initialization cycles are
required instead of eight RAS cycles.
AC characteristics assume t
T
= 2 ns.
V
IH
(min) and V
IL
(max) are reference levels for measuring the timing of input signals. Transition times
are measured between V
IH
(min) and V
IL
(max).
Assumes that t
RCD
≤
t
RCD
(max), t
RAD
≤
t
RAD
(max). If t
RCD
and/or t
RAD
is greater than the maximum recom-
mended value shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the value
shown.
If t
RCD
≥
t
RCD
(max), t
RAD
≥
t
RAD
(max), and t
ASC
≥
t
AA
- t
CAC
- t
T
, access time is t
CAC
.
If t
RAD
≥
t
RAD
(max) and t
ASC
≤
t
AA
- t
CAC
- t
T
, access time is t
AA
.
Measured with a load equivalent to two TTL loads and 100 pF.
t
OFF
is specified that output buffer change to high-impedance state.
Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. t
RCD
(max) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
t
RCD
(min) = t
RAH
(min)+ 2 t
T
+ t
ASC
(min).
Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. t
RAD
(max) is specified as a
reference point only; if t
RAD
is greater than the specified t
RAD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
Either t
RRH
or t
RCH
must be satisfied for a read cycle.
t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min) the data output pin will remain High-Z state
through entire cycle.
t
CPA
is access time from the selection of a new column address (caused by changing CAS from “L” to
“H”). Therefore, if t
CP
become long, t
CPA
also become longer than t
CPA
(max).
Assumes CAS-before-RAS refresh cycle.
Assumes CAS-before-RAS Self Refresh cycle.
Assumes test mode function.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
*10.
*11.
*12.
*13.
*14.
*15.
*16.
*17.
*Source: See MB814400C Data Sheet for details on the electricals.
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