
MB86296S<Coral-PA> iv
Specification Manual Rev0.1
CONTENTS
1. GENERAL
1.1 Preface ...........................................................................................................................................1
1.2 Features .........................................................................................................................................2
1.3 Block Diagram ................................................................................................................................3
1.4 Functional Overview.......................................................................................................................4
1.4.1 Host CPU interface ..................................................................................................................4
1.4.2 External memory interface.......................................................................................................5
1.4.3 Display controller......................................................................................................................6
1.4.4 Video capture function..............................................................................................................8
1.4.5 Geometry processing...............................................................................................................9
1.4.6 2D Drawing.............................................................................................................................10
1.4.7 3D Drawing.............................................................................................................................12
1.4.8 Special effects........................................................................................................................13
1.4.9 Others.....................................................................................................................................15
2. PINS
2.1 Signals..........................................................................................................................................16
2.1.1 Signal lines.............................................................................................................................16
2.2 Pin Assignment.............................................................................................................................17
2.2.1 Pin assignment diagram.........................................................................................................17
2.2.2 Pin assignment table..............................................................................................................18
2.3 Pin Function..................................................................................................................................26
2.3.1 Host CPU interface ................................................................................................................26
2.3.2 Video output interface ............................................................................................................28
2.3.3 Video capture interface ..........................................................................................................30
2.3.4 I
2
C interface............................................................................................................................31
2.3.5 Graphics memory interface....................................................................................................32
2.3.6 Clock input..............................................................................................................................33
2.3.7 Test pins .................................................................................................................................34
2.3.8 Reset sequence .....................................................................................................................34
2.3.9 How to switch internal operating frequency...........................................................................34
3. PROCEDURE OF THE HARDWARE INITIALIZATION
3.1. Hardware reset.............................................................................................................................35
3.2. Re-reset........................................................................................................................................35
3.3. Software reset ...........................................................................................................................35
4.
HOST INTERFACE
4.1
Standard PCI Slave Accesses ....................................................................................................36
4.1.1 PCI Slave Write......................................................................................................................36
4.1.2 PCI Slave Read......................................................................................................................36
4.2
Burst Controller Accesses (including PCI Master)......................................................................36
4.2.1
Transfer Modes .....................................................................................................................37
4.2.2
Burst Controller Control/Status..............................................................................................38
4.3
FIFO Transfers............................................................................................................................39
4.4
GPIO/Serial Interface..................................................................................................................39
4.4.1 GPIO .......................................................................................................................................39
4.4.2 Serial Interface........................................................................................................................39
4.5
Interrupt.......................................................................................................................................40
4.5.1 Address Error Interrupt............................................................................................................40
4.6
Memory Map...............................................................................................................................41
5.
I
2
C Interface Controller
1
16
35
36
43