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參數(shù)資料
| 型號： | MB86604LPFV |
| 元件分類： | 總線控制器 |
| 英文描述： | SCSI BUS CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 45/56頁 |
| 文件大?。?/td> | 382K |
| 代理商： | MB86604LPFV |
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5
MB86604L
Note: The SCSI interface input/output pins can be connected to a single-end type SCSI bus.
2.
MPU Interface
(Continued)
Phase name
MSG
C/D
I/O
Transfer direction
Initiator
Target
Data-out phase
H
→
Data-in phase
H
L
←
Command phase
H
L
H
→
Status phase
H
L
←
Message-out phase
L
H
→
Message-in phase
L
←
Pin
number
Symbol*
Pin name
I/O
Function
77
CS0
Chip select 0
I
This is a chip select 0 pin used by MPU to select the SPC as an
I/O device. This is an active-low pin.
80
CS1
Chip select 1
I
This is a chip select 1 pin to select when MPU inputs/outputs the
data on DMA bus through SPC. This is an active-low pin.
98, 97, 96,
95, 94, 93,
92, 91
D15
to
D8
Data 15
to
data 8
I/O
These pins are for the upper byte and parity bit of MPU data bus.
When the CS0 input is valid, these pins serve as I/O ports for the
SPC internal registers. When the CS1 input is valid, these pins
serve as I/O ports for the DMA bus data.
99
UDP
Upper data
parity
89, 88, 87,
86, 85, 84,
83, 82
D7
to
D0
Data 7
to
data 0
I/O
These pins are for the lower byte and parity bit of the MPU data
bus. When the CS0 input is valid, these pins serve as I/O ports
for the SPC internal registers. When the CS1 input is valid, these
pins serve as I/O ports for the DMA bus data.
81
LDP
Lower data
parity
76, 75, 74,
73, 72
A4
to
A0
Address 4
to
address 0
I
These are address input pins to select the SPC internal
registers.
2RD
(R/W)
Read
(read/write)
I
In the 80-series mode, this is a read signal input pin (IORD or
RD) that MPU reads the SPC. This read signal pin is an active-
low. In the 68-series mode, this pin functions as the control
signal input (R/W) to control the read/write operation to the SPC.
In the read operation, this pin is an active-high. In the write
operation, this pin is an active-low.
1WR
(LDS)
Write
(lower data
strobe)
I
In the 80-series mode, this pin is a write signal input pin (IOWR
or WR) that MPU writes to the SPC. This write signal input pin is
active-low. In the 68-series mode, this pin function as the lower
data strobe signal input (LDS) that MPU outputs when the lower
byte of data bus is valid. The LDS pin is an active-low.
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