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參數(shù)資料
| 型號(hào)： | MB86606A |
| 廠商： | Fujitsu Limited |
| 英文描述： | FAST-20 SCSI Protocol Controller |
| 中文描述： | 快20的SCSI協(xié)議控制器 |
| 文件頁數(shù)： | 11/64頁 |
| 文件大?。?/td> | 605K |
| 代理商： | MB86606A |
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11
MB86606A
3. 16-Bit Bus Mode – DMA Interface
Pin no.
Pin name
I/O
Function
130
DREQ
O
This is used to output DMA transfer request signals to the
DMAC.
DMA data transfer between the SPC and memory is
requested.
129
DACK
I
This is used to input DMA-enabling signals from the DMAC.
When the DMA enabling signal is active, DMA reading and
writing are executed.
138, 139, 141 to 144, 1, 3
136
DMD15 to 8
UDMDP
I/O
Upper byte and parity of DMA data bus
When CS1 input valid:
The MPU data bus is directly
connected.
When 80-series mode: The 2nd data is input/output.
When 68-series mode: The 1st data is input/output.
4, 5, 7, 9 to 11, 13, 14
15
DMD7 to 0
LDMDP
I/O
Lower byte and parity of DMA data bus
When CS1 input valid:
The MPU data bus is directly
connected.
When 80-series mode: The 1st data is input/output.
When 68-series mode: The 2nd data is input/output.
135
DMRD (DMR/W)
I
In 80-series mode: This is used to input the IORD or RD
signal for outputting data from the SPC
to the DMA bus.
In 68-series mode: This is used to input the R/W control
signal for outputting and inputting data
from the DMAC to the SPC.
133
DMWR (DMLDS)
I
In 80-series mode: This is used to input the IOWR or WR
signal for inputting data from the DMA
bus to the SPC.
In 68-series mode: This is used to input the LDS signal
output by the DMAC when the lower
byte of the DMA data bus is valid.
132
DMBHE (DMUDS)
I
In 80-series mode: This is used to input the BHE signal
output by the DMAC when the upper
byte of the DMA data bus is valid.
In 68-series mode: This is used to input the UDS signal
output by the DMAC when the upper
byte of the DMA data bus is valid.
125
DMA0
I
This is used to input the address data A0 signal output by
the DMAC in the 80-series mode.
In 68-series mode:
Connect to power supply pin (V
DD
).
126
TP
(Transfer
permission)
I
This is used to input DMA-transfer-enabling signals.
When the TP signal is active, the SPC performs the DMA
transfer.
When this signal becomes inactive during DMA transfer, the
transfer stops temporarily at the block boundary.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB86606APMT2 | FAST-20 SCSI Protocol Controller |
| MB86606 | FAST-20 SCSI Protocol Controller(FAST-20 SCSI 協(xié)議控制器) |
| MB86612 | IEEE 1394 Bus Controller (for MPEG, DVC) |
| MB86612PBT | IEEE 1394 Bus Controller (for MPEG, DVC) |
| MB86612PFV | IEEE 1394 Bus Controller (for MPEG, DVC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86606APMT2 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:FAST-20 SCSI Protocol Controller |
| MB86612 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for MPEG, DVC) |
| MB86612PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for MPEG, DVC) |
| MB86612PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for MPEG, DVC) |
| MB86613 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
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