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參數(shù)資料
| 型號： | MB86831-66PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件頁數(shù)： | 26/56頁 |
| 文件大?。?/td> | 266K |
| 代理商： | MB86831-66PFV-G |
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SPARClite Series 32-Bit RISC Embedded Processor
32
Fujitsu Microelectronics, Inc.
Load (16-bit bus width)
When the bus is programmed to be 16 bits wide (dened by the chip
select region) every load will transfer 32 bits. Figure 17 on page 40
shows a load (byte, half word, word) operating with an 16-bit bus.
For the load byte and load half word instructions, the IU masks off
the bits which are not required. For a 16-bit bus, the -BE2 pin is
dened to be theADR1 address bit. -BE<1:0> and -BE3 are unused
and driven low.
Load (8-bit wide bus)
When the bus is programmed to be 8 bits wide (dened by the chip
select region) every load will transfer 32 bits. Figure 15 on page 39
shows a load (byte, half word, word) operating with an 8-bit bus.
For the load byte and load half word instructions, the IU masks off
the bits which are not required. For an 8-bit bus -BE<3:2> are the
ADR<0:1> address bits, respectively. -BE<1:0> are unused and
are driven to undened states.
Load with Exception
If the external memory system sees a memory exception it can
terminate the current memory transaction by asserting the
–MEXC and –READY signals.The data on the data bus is ignored.
See Figure 8 on page 35.
Store
Unlike loads, which always transfer 32 bits, only the minimum
number of bus cycles required to complete the store are performed.
For example, only two bus cycles are required to do a half-word
store on an 8-bit bus.
Store (32-bit bus width)
A write transaction begins with the BIU asserting –AS, to indicate
the start of a new bus transaction.The –AS signal is de-asserted
after one clock.At the same time, theADR<27:2> andASI<3:0>
pins are driven with the location to be written while the D<31:0>
pins carry the write data. –BE<3:0> indicate which bytes to write
for a given type of store operation (byte, half-word, or word).
The BIU drives the RDWR signal low to indicate a write
transaction. See Figure 9 on page 35.
The external memory system responds with the assertion of
–READY when it has stored the data. Or, if the internal wait-state
generator is enabled, -READY is generated internally.
A store double operation is treated as two back-to-back word
writes.
Store (16-bit wide bus)
Stores to 16-bit memory are sized to the bus.That is, for a 16-bit
bus, a store word requires two cycles while a store halfword or store
byte requires a single cycle. Figure 18 on page 40 shows the timing
for different types of stores. For a 16-bit bus, -BE2 is driven with
ADR<1>. -BE3 is unused and is driven low. -BE<1:0> are dened
to be the high and low order byte enables, respectively.
Store (8-bit wide bus)
Stores to 8-bit memory are sized to the bus.That is, for a 8-bit bus, a
store word requires four cycles, a store halfword requires two cycles,
and store byte requires a single cycle. Figure 17 on page 40 shows
the timing for different types of stores. For an 8-bit bus,
-BE<2:3> are driven withADR<1:0>. -BE<1:0> are unused and
are driven to undened states.
Store with Exception
If an access exception occurs on a write, the external memory system
can terminate the current memory transaction by asserting the –
MEXC and –READY signals.The external memory system is
expected to ignore the data on the data bus in this situation.
See Figure 10 on page 36.
Atomic Load Store
An atomic load store executes as a load followed by a store with no
operation allowed in between.The –LOCK signal is asserted to
indicate that the bus is being used for more than one external
memory operation. See Figure 11 on page 36.
There is one idle cycle between the termination of the read and the
beginning of the write to provide time for changing the direction of
the data bus drivers.
External Bus Request and Grant
Any external device can request ownership of the bus by asserting the
–BREQ signal. When control of the bus is granted, the BIU asserts
the –BGRNT signal and oats its bus drivers. In the following cycle,
the external device can begin its transaction.
On completion of its transaction the external device de-asserts the
–BREQ signal.The BIU responds by de-asserting the –BGRNT
signal in the following cycle. See Figure 12 on page 37.
A separate signal, –PBREQ, is asserted by the processor to indicate
to a bus arbiter that it has a pending bus transaction.
This allows the bus to be allocated based on demand.The signal,
-PBREQ, is asserted when the write buffer is full or the CPU is
doing an instruction or data fetch.The CPU is the default owner of
the bus.
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PDF描述 |
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| MB86832-80PFV-G | 32-BIT, 80 MHz, RISC PROCESSOR, PQFP176 |
| MB86832-66PFV-G | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| MB86860 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86831-80PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86831PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832-100PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832-66PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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