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參數(shù)資料
| 型號： | MB86831-66PFV-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件頁數(shù)： | 27/56頁 |
| 文件大小： | 266K |
| 代理商： | MB86831-66PFV-G |
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MB86831
Fujitsu Microelectronics, Inc.
33
8- and 16-Bit Bus Modes
Any chip select (-CS<5:0>) can be mapped to 8-, 16-, or 32-bit bus
width, however -CS4 and -CS5 cannot be mapped to 8-bit bus width
if the DRAM controller is enabled. Memory width for -CS0 is
selected at system reset with the -BMODE8 and -BMODE16 signals.
Table 13, below shows the bus width options available for the -CS0
area. Memory width for the -CS<5:1> areas is programmed by two
bits for each chip select in the Bus Width and Cacheable Register.
Table 14, also below, shows the programming bits and the
corresponding bus width of each chip select.
Table 13. Bus Width Control of -CS0
Table 14. Bus Width Control Bits of -CS1 to -CS5
8- and 16-bit transactions are similar to 32-bit transactions except
that –AS is asserted only once at the beginning of the bus cycle for a
load operation, and –READY is asserted at the end of each byte or
halfword transfer.The –BE<3:0> signals indicate the byte or
halfword being read or written (see Figure 15 on page 39 through
Figure 18 on page 40).
For 32-bit writes to 8- or 16-bit memory and 16-bit writes to 8-bit
memory, the BIU drives -BE<2:3> asADR<1:0>, and initiates
multiple transactions.
When the internal DRAM controller is enabled, 8-, 16-, and 32-bit
bus width are available for -CS0 through -CS3, and only 16- or 32-
bit memory bus are available for -CS4 and -CS5, depending on the
DRAM bus width.
Burst Mode Transactions
For systems that can support burst mode transactions, the DRAM
controller can be programmed to support four-word bursts. When
burst mode is enabled, –BMREQ is asserted at the beginning of each
bus cycle for which a burst transfer is allowed (see Table 15, below).
If the memory system can support a burst for the current bus
address, the memory system asserts –BMACK to begin the burst
transaction. –BMACK is asserted on the rst word of the burst
transaction only. –READY is asserted for each word of the burst.
Systems that do not support burst mode for the current address
should not assert –BMACK. If either –BMREQ or -BMACK is not
asserted for a transaction, only one word is transferred for each
assertion of -AS.
Table 15. ADR<3:2> Sequence in Burst Mode
Selection of Hyperpage Mode (EDO Mode)
By setting bit 8 of the DRAM Bank Conguration Register,
hyperpage DRAM can be connected and controlled. However, if the
DRAM Burst Enable Bit (bit 7 of the System Support Control
Register) is clear, access timing is controlled in the same cycle as
normal page-mode DRAM.
When the DRAM Burst Enable Bit is set and hyperpage is enabled,
hyperpage burst access is performed. In this case,ADR<3:2> is not
a value from the CPU but is generated by the DRAM controller
itself. Because data is driven before it is received from the DRAM,
the CAS cycle time can be shortened compared to the normal page
mode burst transactions.
-BMODE16
-BMODE8
Bus Width
0
Illegal
0
1
16-bit Bus
1
0
8-bit Bus
1
32-bit Bus
BW1
BW0
Bus Width
0
32-bit Bus
0
1
8-bit Bus
1
0
16-bit Bus
1
Illegal
Bus Cycle 1
Bus Cycle 2
Bus Cycle 3
Bus Cycle 4
00
01
10
11
01
00
11
10
11
00
01
11
10
01
00
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB86832-80PFV-G | 32-BIT, 80 MHz, RISC PROCESSOR, PQFP176 |
| MB86832-66PFV-G | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| MB86860 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| MB86931-20ZF-G | 32-BIT, 20 MHz, RISC MICROCONTROLLER, CQFP256 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86831-80PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86831PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832-100PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832-66PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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