SPARClite Series 32-Bit RISC Embedded Processor
46
Fujitsu Microelectronics, Inc.
Electrical Characteristics
Table 17. Absolute Maximum Ratings
VSS=0V
Notes:
1.
Stresses above those listed under Absolute Rating may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other condition above those indicated in the operation section of this specication is not implied. Exposure to Absolute Maximum
Ratings conditions for extended periods may affect device reliability.
Recommended Connections:
1.
Power and ground connections must be made to multiple VDD and VSS pins. Every MB86832 based circuit board should include power (VDD) and ground
(VSS) planes for power distribution. Every VDD pin must be connected to the power plane, and every VSS pin must be connected to the ground plane. Pins
identied as “N.C.” must not be connected in the system.
2.
Liberal decoupling capacitance should be placed near the MB86832. The processor can cause transient power surges when multiple output buffers tran-
sition, particularly when connected to large capacitive loads.
3.
Low inductance capacitors and interconnections are recommended for best high frequency electrical performance. Inductance can be reduced by short-
ening the board traces between the processor and decoupling capacitors as much as possible. Capacitors specically designed for the QFP package offer
the least inductance.
4.
For reliable operation, alternate bus masters must drive any pins that are oated by the MB86833 when it has granted the bus, in particular the
-LOCK, ADR<27:2>, ASI<3:0>, -BE<3:0>, D<31:0>, -AS and RDWR signals must be driven by alternate bus masters. These pins are normally driven by
the processor during active and idle bus states and don’t require external pullups (except for -BE2, which becomes an address input). N.C. pins must
always remain unconnected.
Table 18. Recommended Operating Conditions
The MB86832 can be used with a 5V system or a 3.3V system interface:
5V System Interface
IO_VDD = 5V andVDD = 3.3V
Two Power Supplies
3.3V System Interface
IO_VDD =VDD = 3.3V
Single Power Supply
Symbol
Rating
Min.
Max.
Units
IO_VDD
Power Supply Voltage (I/O)
-0.5
6
V
VDD
Power Supply Voltage (Core)
-0.5
4
V
V1
Input Voltage
-0.5
IO_VDD+0.5
V
TSTG
Storage Ambient Temperature
-55
125
°C
TBIAS
Temperature during Bias
0
70
°C
-
Overshoot
IO_VDD+1.0V or less (50ns or less)
-
Undershoot
VSS-1.0V or less (50ns or less)
Symbol
Rating
Min.
Typ.
Max.
Units
IO_VDD
Power Supply Voltage (I/O = 5V)
4.75
5.0
5.25
V
Power Supply Voltage (I/O = 3.3V)
3.0
3.3
3.6
V
VDD
Power Supply Voltage (Core)
3.0
3.3
3.6
V
VIL
Low Level Input Voltage
0
-
VDD0.25
V
VIH
High Level Input Voltage
VDD0.65
-
IO_VDD
V
Topr
Operating Temperature
0
25
70
°C