參數(shù)資料
型號: MB86834-120PFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-bit Embedded Controller
中文描述: 32-BIT, 120 MHz, RISC MICROCONTROLLER, PQFP176
封裝: 24 X 24 MM, PLASTIC, QFP-176
文件頁數(shù): 36/82頁
文件大小: 1373K
代理商: MB86834-120PFV
MB86830 Series
36
(Continued)
(V
DD3
=
3.3 V
±
0.3 V, V
SS
=
0.0 V, T
A
=
0
°
C to
+
70
°
C)
Value
V
DD5
= 5.0 V ± 5%
V
DD5
= 3.3 V ± 0.3 V
Min.
Max.
15
2
15
2
15
2
15
2
Asynchronous
Asynchronous
2
×
P
+
10
2
×
P
+
10
2
×
P
+
10
2
×
P
+
10
P:Period (Cycle time)
* : RDYOUT# at the external ready mode is provided for from READY# input.
Notes
Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise
noted.
Each voltage value is based on the GND (V
SS
=
0.0 V) level. The timing measurement reference point is 1.5
V, the input level is 0.4 to 2.4 V, and the input rise time and fall time are 2 ns or less.
Do not leave more than one output pins short-circuited for 1 second or more.
The external output load capacitance is 30 pF.
The specifications of pins other than those pins designated as asynchronous inputs and than the RDYOUT#
pin in external ready mode are determined by the rising edge of the external clock (CLKIN).
These specifications are subject to change for improvement.
The reset period requires at least 4 CLKIN cycles. The PLL oscillation stabilization delay time requires at least
4000 clock (CLKIN) pulses. For 40-MHz (25 ns) clock input, for example, the reset signal must therefore be
negated 100
μ
s later.
Classifica-
tion
Parameter
Symbol
Unit
Min.
2
2
2
2
Asynchronous
Asynchronous
Max.
15
15
15
15
DRAMC
output
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Delay time
Hold time
Setup time
Hold time
“H” level period
“L” level period
RAS0# to RAS3#
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS0# to CAS3#
DWE0# to DWE3#
DOE#
IRC input
IRQ15 to IRQ8
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