參數(shù)資料
型號(hào)： MB86977
廠商： Fujitsu Limited
英文描述： IP PACKET FORWARDING ENGINE
中文描述： IP數(shù)據(jù)包轉(zhuǎn)發(fā)引擎
文件頁(yè)數(shù)： 6/30頁(yè)
文件大?。?/td> 149K
代理商： MB86977
MB86977
6
MII Interface
Pin No.
SMI interface
Pin No.
Pin Name
I/O
Description
134
120
72
86
TX_CLK_W
TX_CLK_D
TX_CLK_0
TX_CLK_1
I
TX CLOCK
This clock from the PHY device provides the timing reference for
transfer of TX_EN and TXD signals.
The frequency is 25 MHz for 100 Mbps, 2.5 MHz for 10 Mbps.
150 to 153
108 to 111
60 to 63
102 to 105
TXD_W [3 : 0]
TXD_D [3 : 0]
TXD_0 [3 : 0]
TXD_1 [3 : 0]
O
TRANSMIT DATA
The nibble data is transmitted to PHY devices through this
interface.
149
107
59
101
TX_EN_W
TX_EN_D
TX_EN_0
TX_EN_1
O
TRANSMIT ENABLE
Active high signal indicates that TX data is valid.
Synchronous with TX_CLK.
142
128
80
94
RX_CLK_W
RX_CLK_D
RX_CLK_0
RX_CLK_1
I
RX CLOCK
This clock from the PHY device provides the timing reference for
reception.
The frequency is 25 MHz for 100 Mbps, 2.5 MHz for 10 Mbps.
141
127
79
93
RX_ER_W
RX_ER_D
RX_ER_0
RX_ER_1
I
RECEIVE ERROR
Active high signal indicates that an invalid symbol has been
detected within a received packet.This input is ignored when
RX_DV signal of the same interface is inactive.These pins are
used for both RMII and MII modes.
136
122
74
88
RX_DV_W
RX_DV_D
RX_DV_0
RX_DV_1
I
RECEIVE DATA VALID
Active high signal indicates that RXD is valid.
132
118
70
84
CRS_DV_W
CRS_DV_D
CRS_DV_0
CRS_DV_1
I
CARRIER SENSE
Active high signal indicates that either the transmit or receive
medium is not idle. It is not synchronous to any clock.
These pins are used for both RMII and MII modes.
137 to 140
123 to 126
75 to 78
89 to 92
RXD_W [3 : 0]
RXD_D [3 : 0]
RXD_0 [3 : 0]
RXD_1 [3 : 0]
I
RECEIVE DATA
Nibble data from the PHY device.Bits [1:0] are used for both MII
and RMII modes.
133
119
71
85
COL_W
COL_D
COL_0
COL_1
I
COLLISION DETECT
Active high signal indicates that collision has been detected in half
duplex mode. It is valid when TX_EN is active. It is not
synchronous to any clock.
Pin Name
I/O
Description
155
MDCLK
O
MANAGEMENT DATA CLOCK
SMI Clock to PHYs.
162
MDIO
I/O
MANAGEMENT DATA INPUT/OUTPUT
SMI Data to/from PHYs.
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