參數(shù)資料
型號(hào)： MB881822BWQN-G-JN-EFE1
廠商： FUJITSU LTD
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 100 MHz, OTHER CLOCK GENERATOR, PQCC24
封裝： 2.50 X 3.50 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, PLASTIC, QFN-24
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 938K
代理商： MB881822BWQN-G-JN-EFE1
MB88182
22
DS04-29138-5E
(Continued)
(Ta
= 40 °C to + 85 °C, VDD = 1.8 V ± 0.15 V, VDDE = 2.6 V ± 0.1 V, VDP = 2.6 V ± 0.1 V)
*1: Part number: MB881821APVA1/MB881821BPVA1
*2: Part number: MB881822APVA1/MB881822BPVA1
*3 : When K divider parameter = 1 and output frequency is above 50 MHz.
*4 : When K divider parameter
≠ 1, or K divider parameter = 1 and output frequency is 50 MHz or less.
*5 : Duty cycle of the CKREF output depends on the tDCI, input clock duty cycle.
*6 : The wait time for clock stabilization is needed after turning the power on or when changing the setting of ENS/
power down pins. The lock-up time varies depending on the setting value to the respective register. Please
confirm the recommended value with the Fujitsu Semiconductor support tool. Contact the sales representatives
for details on the support tools.
Parameter
Symbol
Pin
Conditions
Value
Unit
Min
Typ
Max
Output clock
duty cycle
tDCC
CLK1*1
VDD
/ 2*3
40
60
%
VDD
/ 2*4
45
55
CLK1*2
VDDE
/ 2*3
40
60
VDDE
/ 2*4
45
55
CLK2,
CLK3,
CLK4
VDDE
/ 2, VDP / 2*3
40
60
VDDE
/ 2, VDP / 2*4
45
55
CKREF
VDP
/ 2tDCI 5*5
tDCI
+ 5*5
Modulation
frequency
FMOD
CLK2,
CLK3,
CLK4
fin/ (224
× L)
( 224
× L )
fin/ (266
× L)
( 266
× L )
fin/ (308
× L)
( 308
× L )
kHz
(clks)
Lock-up time*6
tLK
CLK1
0.3
ms
CLK2,
CLK3,
CLK4
16
ms
Cycle-cycle
jitter
tJC
CLK1,
CLK2,
CLK3,
CLK4
No load
capacitance
100
ps-rms
CKREF
Power down
tRPD
CKREF
tP
× 2 + 2ns
CKREF
Power down
release
tROE
CKREF
tP
× 2 + 2ns
相關(guān)PDF資料
PDF描述
MB881821AWQN-G-JN-ERE1 100 MHz, OTHER CLOCK GENERATOR, PQCC24
MB881822APVA1-GE1 100 MHz, OTHER CLOCK GENERATOR, PBCC20
MB881821BPVA1-G-EFE1 100 MHz, OTHER CLOCK GENERATOR, PBCC20
MB881821BPVA1-G-ERE1 100 MHz, OTHER CLOCK GENERATOR, PBCC20
MB881821APVA1-G-ERE1 100 MHz, OTHER CLOCK GENERATOR, PBCC20
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