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參數(shù)資料
| 型號： | MB881822BWQN-G-JN-EFE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PQCC24 |
| 封裝： | 2.50 X 3.50 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, PLASTIC, QFN-24 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 938K |
| 代理商： | MB881822BWQN-G-JN-EFE1 |
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MB88182
26
DS04-29138-5E
AC characteristics 2 (Serial timing)
(Ta
= 40 °C to + 85 °C, VDD = 1.8 V ± 0.15 V, VDDE = 2.6 V ± 0.1 V)
*: When VDDE
= 1.8 V ± 0.15 V, set the bus load to less than 200 pF and set the bus pull-up resistor value to
1.2 k
Ω or more.
Parameter
Symbol
Pin
Conditions
Value
Unit
Min
Max
SCL clock frequency
fSCL
SCL
0
400
kHz
During data input
set up time
tISU
SDA
100
ns
During data input
hold time
tIH
SDA
0
ns
Noise removal width
tNC
SDA
SCL
100
160
ns
Input hysteresis
VHYS
SDA
SCL
0.3
V
(Repeat) START condition
hold time
tSTAH
SDA
SCL
0.5
μs
Repeat START condition
setup time
tSTASU
SDA
SCL
0.5
μs
SCL clock “L” width
tCL
SCL
1
μs
SCL clock “H” width
tCH
SCL
0.5
μs
STOP condition setup time
tSTOSU
SDA
SCL
0.5
μs
Bus free time between stop
condition and start condition
tBUF
SDA
SCL
1
μs
During bus drive
set up time
tOSU
SDA
Bus load: under 400 pF,
Resistor value for bus
pull-up: at least 750
Ω*
1
μs
During bus drive
hold time
tOH
SDA
0
0.6
μs
During bus drive
fall time
tOF
SDA
300
ns
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