參數(shù)資料
型號(hào): MB88R157APFT-G-XXX-JNE1
廠商: FUJITSU LTD
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 134 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: 4.40 X 3.10 MM, 1.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, TSSOP-8
文件頁(yè)數(shù): 15/28頁(yè)
文件大?。?/td> 844K
代理商: MB88R157APFT-G-XXX-JNE1
MB88R157A
22
DS04–29146–2E
■ LOCK-UP TIME
When the power down control by the VF pin is valid and the power down is controlled, the desired clock
frequency can be gained once the lock up time tLK has elapsed up to its maximum after the VF pin gets to
the H level.
When the modulation control by the VF pin is valid and the modulation is controlled, the frequency set by
the OUT pin output can be set once the lock up time tLK has elapsed up to its maximum after the level for
the VF pin is decided.
Note: The output frequency, the output clock duty cycle, the modulation cycle and the cycle-cycle jitter cannot
be guaranteed until the lock up time has fully elapsed. Therefore, it is recommended to cancel the late
reset of the device or execute other means after the lock up time elapses.
VIH
VIL
XIN
VF
OUT
tLK
(lock-up time)
VIH
VIL
XIN
VF
OUT
tLK
(lock-up time )
tLK
(lock-up time)
相關(guān)PDF資料
PDF描述
MB88R157APFT-G-XXXJNEFE1 134 MHz, OTHER CLOCK GENERATOR, PDSO8
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