參數(shù)資料
型號: MB89626RP-SH
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: Octal Transparent D-type Latches With 3-State Outputs 20-CDIP -55 to 125
中文描述: 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP64
封裝: SHRINK, PLASTIC, DIP-64
文件頁數(shù): 35/61頁
文件大?。?/td> 915K
代理商: MB89626RP-SH
35
MB89620R Series
(3) Clock Timing
(AV
SS
= V
SS
= 0.0 V, T
A
= –40
°
C to +85
°
C)
Value
Unit
Max.
(4) Instruction Cycle
Parameter
Symbol
Pin name
Condition
Remarks
Min.
Clock frequency
F
C
X0, X1
1
10
MHz
Clock cycle time
t
XYCL
X0, X1
100
1000
ns
Input clock pulse width
P
WH
P
WL
X0
20
ns
External clock
Input clock rising/falling
time
t
CR
t
CF
X0
10
ns
External clock
Parameter
Symbol
Value (typical)
Unit
Remarks
Instruction cycle
(minimum execution time)
t
inst
4/F
C
μ
s
t
inst
= 0.4
μ
s when operating at
F
C
= 10 MHz
0.2 V
CC
0.8 V
CC
X0
0.2 V
CC
t
CR
t
CF
0.8 V
CC
0.2 V
CC
X0
X1
X0
X1
When a crystal
or
ceramic resonator is used
When an external clock is used
Open
t
XCYL
P
WL
P
W
X0 and X1 Timing and Conditions
Clock Conditions
相關PDF資料
PDF描述
MB89626RPF Octal Transparent D-type Latches With 3-State Outputs 20-CFP -55 to 125
MB89626RPFM Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-LCCC -55 to 125
MB89627R Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-CDIP -55 to 125
MB89627RPF Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-CFP -55 to 125
MB89627RPFM Dual Positive-Edge-Triggered D-type Flip-Flops With Clear And Preset 20-LCCC -55 to 125
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