5
CHAPTER 1 OVERVIEW
Table 1.2-2 Common specifications for the MB89470 series
Parameter
Specification
CPU functions
Number of instructions: 136 instructions
Instruction bit length: 8-bit
Instruction length : 1 to 3 bytes
Data bit length : 1, 8, or 16-bit
Minimum instruction execution time: 0.32
s/12.5 MHz
Minimum Interrupt processing time: 2.88
s/12.5 MHz
Pe
ri
ph
er
al
f
u
nc
tio
ns
Ports
Output only ports (N-Channel open drain): 7 pins
Input-only ports: 3 pins (1 pin in product with dual clock)
I/O ports (CMOS): 29 pins
Total: 39 pins
21-Bit Time-base
timer
Interrupt period (0.66ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz
Watchdog timer
Reset period (167.8 ms to 335.5 ms) at 12.5 MHz
Reset period (500 ms to 1000 ms) at 32.768 kHz for subclock
Watch prescalar
17 bits
Interrupt cycle: 31.25 ms, 0.25 s, 0.5 s, 1.00 s, 2.00 s, 4.00 s, / 32.768 kHz for subclock
Pulse width count
timer
2 channels
8-bit one-shot timer operation (supports underflow output, operating clock period: 1tinst, 4tinst, 32tinst, external)
8-bit reload timer operation (supports square wave output, operating clock period: 1tinst, 4tinst, 32tinst, external)
8-bit pulse width measurement operation (supports continuous measurement, H width, L width, rising edge to
rising edge, falling edge to falling edge measurement and both edge measurement)
PWM timer
8-bit reload timer operation (supports square wave output, operationg clock period: 1tinst, 8tinst, 16tinst, 64tinst)
8-bit resolution PWM operation
8/16-bit timer/
counter Ch1
Can be operated either as a 2-channel 8-bit timer/counter (Timer 11 and Timer 12, each with its own
independent operating clock cycle), or as one 16-bit timer/counter
In Timer 11 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square
wave output capable
8/16-bit timer/
counter Ch2
Can be operated either as a 2-channel 8-bit timer/counter (Timer 21 and Timer 22, each with its own
independent operating clock cycle), or as one 16-bit timer/counter
In Timer 21 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square
wave output capable
External Interrupt
4 independent channels (selectable edge, interrupt vector, request flag)
5 channels (low level interrupt)
A/D converter
10-bit resolution x 8 channels
A/D conversion function (conversion time: 60 tinst )
Supports repeated activation by internal clock.
UART/SIO 1, 2
Synchronous/asynchronous data transfer capable
(Max. baud rate: 97.656 Kbps at 12.5 MHz)
(7 and 8 bits with parity bit ; 8 and 9 bits without parity bit)
Buzzer output
7 frequency types (FCH/2
12, F
CH/2
11, F
CH/2
10, F
CH/2
9, F
CL/2
5, F
CL/2
4, F
CL/2
3, ) are selectable by software.
Standby modes
Sleep mode, stop mode, subclock mode (dual clock product) and watch mode (dual clock product)
Process
CMOS
Note: tinst is instruction cycle ( execution time ) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock. See 3.6.2.