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CHAPTER 3 CPU
I Speed-shift (main clock speed-switching) function
One of four main clock frequencies can be selected by writing the appropriate values between "00B" and
"11B" to main clock speed select bits of the system clock control register (SYCC: CS1, CS0).
The switch-selected clock signal provides the operating clock for the CPU and peripheral circuits. The
timebase timer and watch prescaler, however, is not affected by the speed-shift (gear) function.
A slower main clock speed reduces power consumption.
I Operation of main clock mode
The main clock and the subclock oscillators both run in the "main-run" mode (the normal main clock
operating mode). The watch prescaler runs on the subclock, but the CPU, timebase timer, and other
peripheral circuits all use the main clock.
When operating in main clock mode, the speed-shift function can be used to select a main clock speed. This
selection affects all circuits that are clocked by the main clock except for the timebase timer. By specifying
a standby mode, you can also go to "main-sleep," or "main-stop" mode.
When the device is reset, the system always starts out in "main-run" mode regardless of how the reset was
initiated. (Each operating mode exited by reset.)
G Changing from main clock mode to subclock mode
Writing "0" to the system clock select bit in the system clock control register (SYCC:SCS) changes the
CPU from the main clock to subclock mode. You can determine which clock is currently being used by
checking the system clock monitor bit of the same register (SYCC: SCM).
Precaution:
If you go to subclock mode immediately after power on, write the software so as to provide a longer
subclock oscillation stabilization wait time than that defined by the watch prescaler.
I Operation of subclock mode
In the normal subclock operating mode ("sub-run" mode), the system runs on the subclock only. The main
clock oscillator is stopped. Using the low speed subclock reduces power consumption.
Other than the timebase timer, all functions operate the same in subclock mode as they do in main clock
mode. If standby mode is specified while operating in subclock mode, the device goes to "sub-sleep," "sub-
stop," or "watch" mode.
G Returning to main clock mode from subclock mode
Writing "1" to the system clock select bit in the system clock control register (SYCC:SCS) returns to main
clock mode from subclock mode.
Operation from the main clock, however, will not start until after the main clock oscillation stabilization
wait time has passed. One of three wait times can be selected by setting the oscillator stabilization wait time
select bits of the system clock control register (SYCC: WT1, WT0).
Precaution:
Do not change the oscillation stabilization wait time select bits (SYCC: WT1, WT0) at the same time
you switch from subclock to main clock mode (SYCC: SCS = 1), or during the oscillator stabilization
wait time. Always check the system clock monitor bit to verify that the main clock is the active
operating clock (SYCC: SCM = 1) before changing these bits.
The device always enters the oscillator stabilization wait time when the system is returned from subclock
mode to main clock mode by reset.