參數(shù)資料
型號: MB89P585BWPFV
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 12.5 MHz, MICROCONTROLLER, PQFP64
封裝: 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 8/37頁
文件大?。?/td> 428K
代理商: MB89P585BWPFV
MB89580B/580BW series
16
The PS register can further be divided into the register bank pointer in the higher 8 bits (RP) and the condition code
register in the lower 8 bits (CCR) . (See the diagram below.)
The RP points to the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule shown next.
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at the time of an interrupt.
H flag
: The flag is set to “1” when an arithmetic operation results in a carry from bit 3 to bit 4 or in a borrow
from bit 4 to bit 3. The bit is cleared to “0” in other instances. The flag is for decimal adjustment
instructions; do not use for other than additions and subtractions.
I flag
: Interrupt is enabled when this flag is set to “1.” Interrupt is disabled when this flag is set to “0.” The
flag is set to “0” when reset.
IL1, 0
: Indicates the level of the interrupt currently enabled. An interrupt is processed only if its level is
higher than the value this bit indicates.
IL1
IL0
Interrupt level
High-low
00
1
Higher
Lower
= no interruption
01
10
2
11
3
PS
RP
CCR
X011XXXXB
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
R4
R3
R2
R1
R0
H
I
IL1
IL0
N
Z
V
C
I-Flag
H-Flag
IL 1,0
Z-Flag
V-Flag
C-Flag
N-Flag
CCR initial value
X : Undefined
Rule for Conversion of Actual Addresses in the General-purpose Register Area
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
A7
A6
A5
A4
A3
A2
A1
A0
A15 A14 A13 A12 A11 A10
A9
A8
Generated addresses
RP higher bits
OP code in lower bits
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