參數(shù)資料
型號(hào): MB90483CPFV
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù): 115/124頁(yè)
文件大?。?/td> 1547K
代理商: MB90483CPFV
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MB90480B/485B Series
90
3.6
2.7
3.0
4
1.5
16
25
16
12
25
8
4
34
8
12.5
16
25
20
32
50
20
6
1.5
9
18
24
5 6
10
40
Range of warranted PLL operation
Normal operating range
Power
supply
voltage
V
CC
(V)
Internal clock fCP (MHz)
Internal operating clock frequency vs. Power supply voltage
Base oscillator frequency vs. Internal operating clock frequency
Base oscillator clock FCH (MHz)
Internal
clock
f
CP
(MHz)
Range of warranted PLL operation
Notes:
For A/D operating frequency, refer to “5. A/D Converter Electrical Characteristics”
Only at 1 multiplied PLL, use with more than fCP = 4 MHz.
No multiplied
*1 : In setting as 1, 2, 3 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP
≤ 25 MHz, set
the PLLOS register to “DIV2 bit
= 1” and “PLL2 bit = 1”.
[Example]
When using the base oscillator frequency of 24 MHz at 1 multiplied PLL :
CKSCR register : CS1 bit
= “0”, CS0 bit = “0”
PLLOS register : PLL2 bit
= “1”
[Example]
When using the base oscillator frequency of 6 MHz at 3 multiplied PLL :
CKSCR register : CS1 bit
= “1”, CS0 bit = “0”
PLLOS register : PLL2 bit
= “1”
*2 : In setting as 2 and 4 multiplied PLL, when the internal clock is used at 20 MHz < fCP
≤ 25 MHz, the following
setting is also enabled.
2 multiplied PLL :
CKSCR register : CS1 bit
= “0”, CS0 bit = “0”
PLLOS register : PLL2 bit
= “1”
4 multiplied PLL :
CKSCR register : CS1 bit
= “0”, CS0 bit = “1”
PLLOS register : PLL2 bit
= “1”
*3 : When using in setting as 6 and 8 multiplied PLL, set the PLLOS register to “DIV2 bit
= 0” and “PLL2 bit = 1”.
[Example]
When using the base oscillator frequency of 4 MHz at 6 multiplied PLL :
CKSCR register : CS1 bit
= “1”, CS0 bit = “0”
PLLOS register : PLL2 bit
= “1”
[Example]
When using the base oscillator frequency of 3 MHz at 8 multiplied PLL :
CKSCR register : CS1 bit
= “1”, CS0 bit = “1”
PLLOS register : PLL2 bit
= “1”
1
× *1
2
× *1,*2
3
× *1
4
×
*1,*2
6
× *3
8
× *3
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