參數(shù)資料
型號: MB90483CPFV
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 51/124頁
文件大?。?/td> 1547K
代理商: MB90483CPFV
MB90480B/485B Series
32
(Continued)
: Interrupt request flag is not cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal (stop request present) .
*1 : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time.
*2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE
= 1) to disable
(TMCSR : INTE
= 0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to 0 : 111B) , then set
the INTE bit to 0.
Note : If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request
flags at the EI2OS/
DMAC interrupt clear signal. Therefore if either of the two sources uses the EI2OS/
DMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corre-
sponding resource should be set to “0” and interrupt requests from that resource should be handled by
software polling.
Interrupt source
Clear of
EI2OS
DMAC
channel
number
Interrupt vector
Interrupt control register
Number
Address
Number
Address
I2C interface
(MB90485B series only)
#39
FFFF60H
ICR14
0000BEH
A/D converter
15
#40
FFFF5CH
Flash write/erase,
timebase timer, watch timer *1
#41
FFFF58H
ICR15
0000BFH
Delay interrupt generator
module
#42
FFFF54H
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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