- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377918 > MB90495G (Fujitsu Limited) 16-bit Proprietary Microcontroller CMOS PDF資料下載
參數(shù)資料
| 型號(hào)： | MB90495G |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller CMOS |
| 中文描述： | 16位微控制器專有的CMOS |
| 文件頁數(shù)： | 59/92頁 |
| 文件大?。?/td> | 450K |
| 代理商： | MB90495G |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當(dāng)前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
MB90495G Series
59
13. ROM Correction Function
In the case that the address of the instruction after the one that a program is currently processing matches the
address configured in the detection address configuration register, the program forces the next instruction to be
processed into an INT9 instruction, and branches to the interrupt process program. Since processing can be
conducted using INT9 interrupts, programs can be repaired using batch processing.
Overview of the ROM Correction Function
The address of the instruction after the one that a program is currently processing is always stored in an
address latch via the internal data bus. ROM correction constantly compares the address stored in the address
latch with the one configured in the detection address configuration register. If the two compared addresses
match, the CPU forcibly changes this instruction into an INT9 instruction, and executes an interrupt processing
program.
There are two detection address configuration registers : PADR0 and PADR1. Each register provides an
interrupt enable bit. This allows you to individually configure each register to enable/prohibit the generation of
interrupts when the address stored in the address latch matches the one configured in the detection address
configuration register.
ROM Correction Block Diagram
Address latch
Stores value of address output to internal data bus.
Address detection control register (PACSR)
Set this register to enable/prohibit interrupt output when an address match is detected.
Detection address configuration register (PADR0, PADR1)
Configure an address with which to compare the address latch value.
AD1E
AD0E
PADR1 (24 bit)
PADR0 (24 bit)
PACSR
Re-
served
Address detection control register (PACSR)
I
Address latch
Detection address configuration register 0
Detection address configuration register 1
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
C
INT9 instruction
(INT9 interrupt generation)
Reserved : Make sure this is always set to “01”
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB90540 | 16-bit Proprietary Microcontroller |
| MB90543GSPF | 16-bit Proprietary Microcontroller |
| MB90543GSPFV | 16-bit Proprietary Microcontroller |
| MB90545 | 16-bit Proprietary Microcontroller |
| MB90545G | 16-bit Proprietary Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB90495G_09 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90497 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller CMOS |
| MB90497G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90497GPF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90497GPFM | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller CMOS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。