參數(shù)資料
型號(hào)： MB90947APF
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 14/57頁(yè)
文件大?。?/td> 1586K
代理商： MB90947APF
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7544 Group
MITSUBISHI MICROCOMPUTERS
21
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e parametric
limits
are
subject
to change.
(3) Event counter mode
Timer A counts signals input from the P00/CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR1 pin input signal can be selected from
rising or falling by the CNTR1 active edge switch bit .
(4) Pulse width HL continuously measurement mode
In the pulse width HL continuously measurement mode, the pulse
width (“H” and “L” levels) input to the P00/CNTR1 pin is measured.
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
The count value when trigger input from the CNTR1 pin is ac-
cepted is retained until Timer A is read once.
Timer A can stop counting by setting “1” to the timer A count stop
bit in any mode.
Also, when Timer A underflows, the timer A interrupt request bit is
set to “1”.
Note on Timer A is described below;
s Note on Timer A
CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit.
When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit is set to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
Fig. 20 Structure of timer A mode register
Fig. 21 Timer count source set register 2
Timer count source set register 2
(TCSS2 : address 002F16, initial value: 0016)
b7
b0
Timer 1 count source selection bits
b1 b0
0
0 : f(XIN)/16
0
1 : f(XIN)/2
1
0 : Ring oscillator output
1
1 : Disable
Timer A count source selection bits
b3 b2
0
0 : f(XIN)/16
0
1 : f(XIN)/2
1
0 : Ring oscillator output
1
1 : Disable
Disable (return “0” when read)
Note : System operates using a ring oscillator as a count source
by setting the ring oscillator to oscillation enabled by bit 3
of CPUM.
Timer A mode register
(TAM : address 001D16, initial value: 0016)
b7
b0
Disable (return “0” when read)
Timer A operating mode bits
b5 b4
0
0 : Timer mode
0
1 : Period measurement mode
1
0 : Event counter mode
1
1 : Pulse width HL continuously
measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge period in period
measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR1 interrupt
Timer A count stop bit
0 : Count start
1 : Count stop
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