參數(shù)資料
型號(hào): MB90F483PFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數(shù): 9/101頁
文件大小: 1129K
代理商: MB90F483PFV
MB90480 Series
15
s BLOCK DIAGRAM
RAM
88
8
P00
P07
P10
P17
P20
P27
P30
P37
P40
P47
P50
P57
P60
P67
P70
P77
P80
P87
ROM
DMA
IN0, IN1
OUT0, OUT1,
OUT2, OUT3,
OUT4, OUT5
8
P90
P97
CS0, CS1,
CS2, CS3
4
PA0
PA3
8
2
X0, X1, RST
X0A, X1A
MD2, MD1, MD0
SIN0
SOT0
SCK0
SIN1, SIN2
SOT1, SOT 2
SCK1, SCK2
AVCC
AVRH
AVSS
ADTG
AN0
AN7
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
PPG0, PPG1
PPG2, PPG3
PPG4, PPG5
IRQ0
IRQ7
8
TIN0
TOT0
Clock control
circuit
Communication
prescaler
UART
I/O expanded serial
interface
× 2 ch
A/D converter
(10-bit)
CPU
F2MC-16LX
Series Core
I/O port
Interrupt controller
8/16-bit PPG
8/16-bit up/down
counter
Chip select
External interrupt
I/O timer
16-bit input capture
× 2
16-bit output compare
× 2
16-bit free run timer
16-bit reload timer
P00 to P07 (8 pins) : with an input pull-up resistance setting register.
P10 to P17 (8 pins) : with an input pull-up resistance setting register.
P40 to P47 (8 pins) : with an open drain setting register.
Except MB90V480 P70 to P75 (8 pins) : with an open drain setting register.
MB90V480
P70 to P75 (6 pins) : with an open drain setting register.
P76,P77 (2 pins) : open drain
Note: In the above diagram, I/O ports share internal function blocks and pins. However, when a set of pins
is used with an internal module, it cannot also be used as an I/O port.
F
2
MC-16LX
Bus
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