參數(shù)資料
型號： MB90F568PMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 38/92頁
文件大?。?/td> 2097K
代理商： MB90F568PMC
MB90560/565 Series
DS07-13715-5E
43
6.
UART
(1) Overview
The UART is a general-purpose serial communications interface for performing synchronous or asynchronous
(start-stop synchronization) communications with external devices.
The interface provides both a bi-directional communication function (normal mode) and a master-slave com-
munication function (multi-processor mode) .
The UART can generate interrupt requests at receive complete, receive error detected, and transmit complete
timings. Also the UART supports EI2OS.
UART functions
The UART is a general-purpose serial communications interface for sending serial data to and from other CPUs
and peripheral devices.
Note : The UART does not add the start and stop bits in clock synchronous mode. In this case, only data is
transmitted.
Function
Data buffer
Full-duplex double-buffered
Transmission modes
Clock synchronous (no start and stop bits)
Clock asynchronous (start-stop synchronization)
Baud rate
Max. 2 MHz (for a 16 MHz machine clock)
Baud rate generated by dedicated baud rate generator
Baud rate generated by external clock (clock input from SCK0 and SCK1 pins)
Baud rate generated by internal clock (clock supplied from 16-bit reload timer)
Eight different baud rate settings are available.
Number of data bits
7 bits (asynchronous normal mode only)
8 bits
Signal format
Non return to zero (NRZ) format
Receive error detection
Framing errors
Overrun errors
Parity errors (not available in multi-processor mode)
Interrupt requests
Receive interrupt (Receive complete or receive error detected)
Transmit interrupt (Transmission complete)
Both transmit and receive support the extended intelligent I/O service (EI2OS) .
Master/slave
communication function
(multi-processor mode)
Used for 1 (master) to n (slave) communications.
(Can only be used as master)
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