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MB90580C Series
51
8.
16-bit Reload Timer
The 16-bit reload timer has three channels, each of which consists of a 16-bit down counter, a 16-bit reload
register, an input pin (TIN), an output pin (TOT), and a control register. The input clock can be selected from
among three internal clocks and one external clock.
(1) Register configuration
Timer control status register (upper)
bit
15
14
13
12
11
10
9
8
Address
: ch0 000049
H
: ch1 00004D
H
: ch2 000051
H
TMCSR0 upper
TMCSR1 upper
TMCSR2 upper
CSL1 CSL0 MOD2 MOD1
Access
(
) (
) (
) (
) (R/W) (R/W) (R/W) (R/W)
(
) (
) (
) (
) (0)
Initial value
(0)
(0)
(0)
Timer control status register (lower)
bit
7
6
5
4
3
2
1
0
Address
: ch0 000048
H
: ch1 00004C
H
: ch2 000050
H
TMCSR0 lower
TMCSR1 lower
TMCSR2 lower
MOD0OUTEOUTLRELD INTE
UF
CNTE TRG
Access
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
Initial value
(0)
(0)
(0)
(0)
16-bit timer register (upper) /16 bit reload register (upper)
bit
Address
: ch0 00004B
H
: ch1 00004F
H
: ch2 000053
H
Access
Initial value
(read)
TMR0 upper
TMR1 upper
TMR2 upper
(write)
TMRLR0 upper
TMRLR1 upper
TMRLR2 upper
15
14
13
12
11
10
9
8
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
16-bit timer register (lower) /16 bit reload register (lower)
bit
Address
: ch0 00004A
H
: ch1 00004E
H
: ch2 000052
H
Access
Initial value
(read)
TMR0 lower
TMR1 lower
TMR2 lower
(write)
TMRLR0 lower
TMRLR1 lower
TMRLR2 lower
7
6
5
4
3
2
1
0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)