參數(shù)資料
型號(hào)： MB90F583CA
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16位微控制器專有
文件頁數(shù)： 57/124頁
文件大?。?/td> 2639K
代理商： MB90F583CA
MB90580C Series
57
11. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to
the F
2
MC-16LX CPU can be generated and cleared by software using this module.
(1) Register configuration
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However,
considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for
register access.
(2) Block Diagram
Delayed interrupt generation/release register
bit
15
(
) (
) (
) (
) (
) (
) (
) (R/W)
(
) (
) (
) (
) (
) (
) (
) (0)
14
13
12
11
10
9
8
Address
: 00009F
H
R0
DIRR
Access
Initial value
Delayed interrupt generation/
release decode
Interrupt
latch
F
2
MC-16LX bus
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