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參數(shù)資料
| 型號： | MB90F822PFM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Scan Test Devices With Octal Bus Transceivers 28-LCCC -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 50/98頁 |
| 文件大?。?/td> | 1415K |
| 代理商： | MB90F822PFM |
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MB90820 Series
50
(4) 16-bit PPG timer (1 channel)
The 16-bit PPG timer 0 is used to provide a PPG signal for waveform generator. (See section “6. 16-bit PPG
Timer”.)
(5) Waveform generator module
The waveform generator consists of three 16-bit timer registers, three 16-bit timer control registers and a wave-
form control register.
With waveform generator, it is possible to generate real time output, 16-bit PPG waveform output, non-overlap
3-phase waveform output for inverter control and DC chopper waveform output.
It is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer. (Dead-time timer
function)
It is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel mode.
(Dead-time timer function)
By detecting realtime output compare match, GATE signal of the PPG timer operation will be generated to
start or stop PPG timer operation. (GATE function)
When a match is detected by real time output compare, the 16-bit timer is activated. The PPG timer can be
started or stopped easily by generating a GATE signal for PPG operation until the 16-bit timer stops. (GATE
function)
Force to stop output waveform using DTTI pin input.
Interrupt is generated when DTTI active or 16-bit timer underflow.
EI
2
OS is supported.
(6) Register configuration
16-bit free-running timer registers
(Continued)
15
14
13
12
11
10
9
8
R/W
0
Address: 00005D
H
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
T15
T14
T13
T12
T11
T10
T09
T08
Address: 00005C
H
7
6
5
4
3
2
1
0
Timer Data Register (Upper)
Timer Data Register (Lower)
TCDT
TCDT
Initial value
Read/write
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Initial value
Read/write
Bit
T07
T06
T05
T04
T03
T02
T01
T00
15
14
13
12
11
10
9
8
R/W
0
Address: 00005F
H
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MSI2
MSI1
MSI0
ICLR
ICRE
Timer Control Status Register (Upper)
Initial value
Read/write
Bit
TCCSH
ECKE
IRQZF IRQZE
Address: 00005E
H
7
6
5
4
3
2
1
0
Timer Control Status Register (Lower)
TCCSL
Bit
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Initial value
Read/write
BFE
STOP
MODE
SCLR
CLK2
CLK1
CLK0
X
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