參數(shù)資料
型號(hào): MB90F822PFM
廠(chǎng)商: Electronic Theatre Controls, Inc.
英文描述: Scan Test Devices With Octal Bus Transceivers 28-LCCC -55 to 125
中文描述: 16位微控制器專(zhuān)有
文件頁(yè)數(shù): 63/98頁(yè)
文件大小: 1415K
代理商: MB90F822PFM
MB90820 Series
63
10. DTP/External Interrupts
The DTP/external interrupt circuit is activated by the signal supplied to a DTP/external interrupt pin. The CPU
accepts the signal using the same procedure it uses for normal hardware interrupts and generates external
interrupts or activates the extended intelligent I/O service (EI
2
OS).
Features of DTP/External Interrupt :
Total 8 external interrupt channels.
Two request levels (“H” and “L”) are provided for the intelligent I/O service.
Four request levels (rising edge, falling edge, “H” level and “L” level) are provided for external interrupt requests.
(1) Register configuration
15
14
13
12
11
10
9
8
R/W
0
Address: 0000031
H
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DTP/Interrupt Source Register
EIRR
Initial value
Read/write
Bit
Address: 000030
H
7
6
5
4
3
2
1
0
DTP/Interrupt Enable Register
ENIR
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Initial value
Read/write
EN7
EN6
EN3
EN2
EN1
EN0
EN5
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
EN4
15
14
13
12
11
10
9
8
R/W
0
Address: 0000033
H
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Request Level Setting Register (Upper)
ELVRH
Initial value
Read/write
Bit
Address: 000032
H
7
6
5
4
3
2
1
0
Request Level Setting Register (Lower)
ELVRL
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Initial value
Read/write
LB3
LA3
LB1
LA1
LB0
LA0
LB2
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
LA2
相關(guān)PDF資料
PDF描述
MB90F822PFV Scan Test Devices With Octal Bus Transceivers 24-CDIP -55 to 125
MB90F823PF Scan Test Devices With Octal Bus Transceivers 28-LCCC -55 to 125
MB90F823PFM Scan Test Devices With Octal Bus Transceivers 24-CDIP -55 to 125
MB90F823PFV 10-Bit Buffers/Drivers With 3-State Outputs 28-LCCC -55 to 125
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