參數(shù)資料
型號: MB90F823PFV
廠商: Electronic Theatre Controls, Inc.
英文描述: 10-Bit Buffers/Drivers With 3-State Outputs 28-LCCC -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 24/98頁
文件大?。?/td> 1415K
代理商: MB90F823PFV
MB90820 Series
24
(Continued)
Address
Abbreviation
Register
Byte
access
Word
access
Resource name
Initial
value
000050
H
000051
H
000052
H
000053
H
000054
H
000055
H
000056
H
000057
H
000058
H
000059
H
00005A
H
00005B
H
00005C
H
00005D
H
TMRR0
16-bit timer register 0
R/W
Waveform generator
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
00000000
B
00000000
B
00000000
B
00000000
B
11111111
B
11111111
B
00000000
B
00000000
B
TMRR1
16-bit timer register 1
R/W
TMRR2
16-bit timer register 2
R/W
DTCR0
DTCR1
DTCR2
SIGCR
16-bit timer control register 0
16-bit timer control register 1
16-bit timer control register 2
Waveform control register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CPCLRB /
CPCLR
Compare clear buffer register/
Compare clear register (lower)
R/W
16-bit free-running
timer
TCDT
Timer register (lower)
R/W
00005E
H
TCCSL
Timer control status register
(lower)
Timer control status register
(upper)
R/W
R/W
16-bit free-running
timer
00000000
B
00005F
H
TCCSH
R/W
R/W
X0000000
B
000060
H
000061
H
000062
H
000063
H
000064
H
000065
H
000066
H
000067
H
IPCP0
Input capture data register CH0
R
16-bit input capture
(CH0 to CH3)
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
IPCP1
Input capture data register CH1
R
IPCP2
Input capture data register CH2
R
IPCP3
Input capture data register CH3
R
000068
H
PICSL01
Input capture control status
register (ch0,1) (lower)
PPG output control / Input
capture control status register
(ch0,1) (upper)
Input capture control status
register (ch2, 3) (lower)
Input capture control status
register (ch2, 3) (upper)
R/W
R/W
00000000
B
000069
H
PICSH01
R/W
R/W
00000000
B
00006A
H
ICSL23
R/W
R/W
00000000
B
00006B
H
ICSH23
R
R
XXXXXX00
B
00006C
H
to
00006E
H
Prohibited area
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