參數(shù)資料
型號(hào): MB90F897PMT
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 10-Bit Buffers/Drivers With 3-State Outputs 24-CDIP -55 to 125
中文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48
封裝: 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 31/78頁
文件大?。?/td> 746K
代理商: MB90F897PMT
MB90895 Series
31
3.
Watchdog Timer
The watchdog timer is a 2-bit counter that uses time-base timer or clock timer as count clock. If the counter is
not cleared within an interval time, CPU is reset.
Watchdog timer functions
The watchdog timer is a timer counter that prevents runaway of a program. Once a watchdog timer is activated,
the counter of watchdog timer must always be cleared within a specified time of interval. If specified interval
time elapses without clearing the counter of a watchdog timer, CPU resetting occurs. This is the function of a
watchdog timer.
The interval time of a watchdog timer is determined by a clock cycle, which is input as a count clock. Watchdog
resetting occurs between a minimum time and a maximum time specified.
The output target of a clock source is specified by the watchdog clock selection bit (WTC: WDCS) in the clock
timer control register.
Interval time of a watchdog timer is specified by the time-base timer output selection bit/clock timer output
selection bit (WDTC: WT1, WT0) in the watchdog timer control register.
Interval timer of watchdog timer
Min
HCLK: Oscillation clock ( 4 MHz) , CSCLK: Sub clock (8.192 kHz)
Notes:
If the time-base timer is cleared when watchdog timer count clock is used as time base timer output
(carry-over signal), watchdog reset time may become longer.
When using the sub clock as machine clock, be sure to specify watchdog timer clock source selection bit
(WDCS) in clock timer control register (WTC) at “0,” selecting output of clock timer.
Max
Clock cycle
2
14
±
2
11
/HCLK
2
16
±
2
13
/HCLK
2
18
±
2
15
/HCLK
2
21
±
2
18
/HCLK
Min
Max
Clock cycle
2
12
±
2
9
/SCLK
2
15
±
2
12
/SCLK
2
16
±
2
13
/SCLK
2
17
±
2
14
/SCLK
Approx. 3.58 ms
Approx. 4.61 ms
Approx. 0.457 s Approx. 0.576 s
Approx. 14.33 ms Approx. 18.3 ms
Approx. 3.584 s Approx. 4.608 s
Approx. 57.23 ms Approx. 73.73 ms
Approx. 7.168 s Approx. 9.216 s
Approx.
458.75 ms
Approx.
589.82 ms
Approx.
14.336 s
Approx.
18.432 s
相關(guān)PDF資料
PDF描述
MB90F897S 10-Bit Buffers/Drivers With 3-State Outputs 28-LCCC -55 to 125
MB90F897SPMT 10-Bit Buffers/Drivers With 3-State Outputs 24-CDIP -55 to 125
MB90M405 Octal Edge-Triggered D-type Flip-Flops With Clear 20-CFP -55 to 125
MB90M407 Octal Edge-Triggered D-type Flip-Flops With Clear 20-LCCC -55 to 125
MB90M408 Octal Edge-Triggered D-type Flip-Flops With Clear 20-CDIP -55 to 125
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