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參數(shù)資料
| 型號： | MB90F897PMT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10-Bit Buffers/Drivers With 3-State Outputs 24-CDIP -55 to 125 |
| 中文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 52/78頁 |
| 文件大?。?/td> | 746K |
| 代理商： | MB90F897PMT |
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MB90895 Series
52
CAN controller block diagram
TX
Set and clear reception
buffer and transmission buffer
Set reception
buffer
ID selection
CRC error
Reception
DLC
CRC generation circuit/
error check
Stuffing
error
Reception
shift register
Destuffing/stuffing
error check
Acceptance
filter
Reception
buffer
decision circuit
Reception buffer
RAM address
generation circuit
Reception buffer, transmission buffer,
reception DLC, transmission DLC, ID selection
Arbitration lost
Arbitration
check
Bit error
Bit error
check
ACK error
Acknowledgment
error check
Form error
Form error
check
Input
latch
Pin
BTR
PSC
TS1
TS2
RSJ
TOE
TS
RS
HALT
NIE
NT
NS1,0
CSR
RTEC
BVALR
TREQR
TCANR
TRTRR
RFWTR
TCR
TIER
RCR
RIER
RRTRR
ROVRR
AMSR
AMR0
AMR1
0
1
LEIR
IDR0 to 7
DLCR0 to 7
DTR0 to 7
RAM
RX
IDER
CPU
operation
clock
Prescaler
(dividing by 1 to 64)
Bit timing
generation circuit
Node status
transition interrupt
generation circuit
Node status
transition
interrupt signal
Bus
status
decision
circuit
Idle, interrupt, suspend,
transmit, receive, error,
and overload
Error
control
circuit
Transmission/
reception
sequence
Clear transmission
buffer
Transmission
buffer
decision circuit
Trans-
mission
buffer
Data
counter
Acceptance
filter control
circuit
Trans-
mission
DLC
Bit error, stuff error,
CRC error, frame
error, ACK error
Recep-
tion
DLC
ID
selection
Arbitration
lost
Error frame
generation
circuit
Overload
frame
generation
circuit
Output
driver
Pin
Transmission
buffer
Transmission
shift register
Transmission
DLC
CRC
generation
circuit
Stuffing
ACK
generation
circuit
Set and clear
transmission buffer
Transmission
completion interrupt
generation circuit
Set reception buffer
Trans-
mission
completion
interrupt
signal
Reception completion
interrupt generation
circuit
Reception
completion
interrupt
signal
Operation clock (TQ)
Sync segment
Time segment 1
Time segment 2
F
2
MC-16LX bus
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| MB90F897S | 10-Bit Buffers/Drivers With 3-State Outputs 28-LCCC -55 to 125 |
| MB90F897SPMT | 10-Bit Buffers/Drivers With 3-State Outputs 24-CDIP -55 to 125 |
| MB90M405 | Octal Edge-Triggered D-type Flip-Flops With Clear 20-CFP -55 to 125 |
| MB90M407 | Octal Edge-Triggered D-type Flip-Flops With Clear 20-LCCC -55 to 125 |
| MB90M408 | Octal Edge-Triggered D-type Flip-Flops With Clear 20-CDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MB90F897PMT-GSE1 | 制造商:FUJITSU 功能描述:IC 16BIT MCU CAN 5V SMD LQFP48 |
| MB90F897SPMCR-GSE1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:MCU 16BIT 16LX 64K FLASH 48LQFP 制造商:FUJITSU 功能描述:MCU, 16BIT, 16LX, 64K FLASH, 48LQFP 制造商:FUJITSU 功能描述:IC, 16BIT MCU, F2MC-16LX, 16MHZ, LQFP-48, Controller Family/Series:F2MC-16LX, Core Size:16bit, No. of I/O's:36, Supply Voltage Min:3.5V, Supply Voltage Max:5.5V, Digital IC Case Style:LQFP, No. of Pins:48, Program Memory Size:64KB , RoHS Compliant: Yes 制造商:FUJITSU 功能描述:MCU, 16BIT, 16LX, 64K FLASH, 48LQFP, Controller Family/Series:F2MC-16LX, Core Si |
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| MB90F962SPMCR-GE1 | 制造商:FUJITSU 功能描述:IC MCU 16BIT 16LX 48LQFP |
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