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參數(shù)資料
| 型號(hào)： | MB90F946APF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 25/57頁 |
| 文件大?。?/td> | 1586K |
| 代理商： | MB90F946APF |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7544 Group
MITSUBISHI MICROCOMPUTERS
31
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e parametric
limits
are
subject
to change.
Reset Circuit
The microcomputer is put into a reset status by holding the RE-
SET pin at the “L” level for 2
s or more when the power source
voltage is 4.5 to 5.5 V and XIN is in stable oscillation.
______
After that, this reset status is released by returning the RESET pin
to the “H” level. The program starts from the address having the
contents of address FFFD16 as high-order address and the con-
tents of address FFFC16 as low-order address.
In the case of f(
φ) ≤ 8 MHz, the reset input voltage must be 0.9 V
or less when the power source voltage passes 4.5 V.
Fig. 35 Example of reset circuit
Fig. 36 Timing diagram at reset
(Note)
0.2 VCC
0 V
Poweron
VCC
RESET
VCC
RESET
Power source
voltage
detection circuit
Power source
voltage
Reset input
voltage
Note : Reset release voltage Vcc = 4.5 V
Data
Address
8-13 clock cycles
Reset address from the
vector table
1 : A built-in ring oscillator applies about RING2 MHz,
φ250 kHz frequency clock
at average of Vcc = 5 V.
2 : The mark “?” means that the address is changeable depending on the previous state.
3 : These are all internal signals except RESET.
Notes
??
FFFC
FFFD
ADH,ADL
??
?
??
ADL
ADH
??
?
Clock from built-in
ring oscillator RING
φ
RESET
RESETOUT
SYNC
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