SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7544 Group
MITSUBISHI MICROCOMPUTERS
37
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e parametric
limits
are
subject
to change.
Fig. 46 State transition
Stop modeWait mode
WIT
instruction
Oscillation stop detection circuit valid
CPUM4
←12
MISRG1
←12
Interrupt
STP
instruction
WIT
instruction
Interrupt
MISRG1
←02
CPUM3
←12
CPUM3
←02
CPUM76
←102
CPUM76
←002
012
112
(Note 2)
CPUM4
←02
MISRG1
←12
MISRG1
←02
Reset released
State 1
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
Ring oscillator stop
State 2
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
Ring oscillator enabled
State 3
Operation clock source:
Ring oscillator (Note 3)
f(XIN) oscillation enabled
Ring oscillator enalbed
State 4
Operation clock source:
Ring oscillator (Note 3)
f(XIN) oscillation stop
Ring oscillator enalbed
Notes on switch of clock
(1) In operation clock source = f(XIN), the following can be
selected for the CPU clock division ratio.
q f(XIN)/2 (high-speed mode)
q f(XIN)/8 (middle-speed mode)
q f(XIN) (double-speed mode, only at a ceramic oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3’ to state 2’ after stabilizing XIN oscillation.
(3) In operation clock source = ring oscillator, the middle-
speed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2
→ state 3 → state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
CPUM76
→ 102 (State 2 → state 3)
NOP instruction
CPUM4
→ 12 (State 3 → state 4)
Double-speed mode at ring oscillator: NOP 3
High-speed mode at ring oscillator: NOP 1
Middle-speed mode at ring oscillator: NOP 0
Reset state
CPUM76
←102
CPUM76
←002
012
112
(Note 2)
State 2’
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
Ring oscillator enabled
State 3’
Operation clock source:
Ring oscillator (Note 3)
f(XIN) oscillation enabled
Ring oscillator enalbed