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參數(shù)資料
| 型號： | MB90M408APF |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Original Microcontroller |
| 中文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 28/64頁 |
| 文件大?。?/td> | 310K |
| 代理商： | MB90M408APF |
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MB90M405 Series
28
4.
Watchdog Timer
The watchdog timer is a two-bit timer that uses the output of the timebase timer as a count clock. When the
watchdog timer is started, if it is not cleared within the set interval, the CPU is reset.
Watchdog Timer Function
The watchdog timer detects runaway programs. When the watchdog timer is started, it must be cleared within
a set interval. If a program enters an infinite loop, or for some other reason the watchdog timer is not cleared
within the minimum time, a watchdog reset is generated to the CPU, sending it to a reset state. The watchdog
timer interval is set by the interval time setting bits (WT1 and WT0) of the watchdog timer control register (WDTC) .
* : When oscillator clock frequency is 4 MHz.
Reference : After the watchdog timer is started, it can be halted via a power-on reset, or a reset by the watchdog
timer. While an external reset, internal reset, setting the watchdog control bit (WTE) of the watchdog
timer control register (WDTC) , or going to sleep or stop mode can clear the watchdog timer, these
actions will not change the watchdog function setting, or halt the watchdog timer.
Note: The watchdog timer is made up of a two-bit timer that counts the carry signal of the timebase timer. Because
the watchdog timer uses the carry signal of the timebase timer, if the timebase timer is cleared, then the
watchdog reset interval may be longer than the set time.
Block Diagram of Watchdog Timer
WT1
WT0
Interval Times
Minimum*
Maximum*
Oscillator clock cycles
2
14
±
2
11
cycles
2
16
±
2
13
cycles
2
18
±
2
15
cycles
2
21
±
2
18
cycles
0
0
Approx. 3.59 ms
Approx. 4.61 ms
0
1
Approx. 14.33 ms
Approx. 18.43 ms
1
0
Approx. 57.34 ms
Approx. 73.74 ms
1
1
Approx. 458.76 ms Approx. 589.82 ms
PONR
WRST ERST SRST WTE
WT1
WT0
×
2
1
×
2
2
×
2
8
×
2
9
×
2
10
×
2
11
×
2
12
×
2
13
×
2
14
×
2
15
×
2
16
×
2
17
×
2
18
2
4
Watchdog timer control register (WDTC)
Watchdog timer
Sleep mode start
Hold status start
Stop mode start
Timer clear
control
circuit
Count clock
selector
Clear
Clear
Clear
Clear and start
2-bit
counter
Over
flow
Watchdog reset
generation circuit
To inter reset
generation circuit
(Timebase timer counter)
Main clock
: Undefined bit
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