MB90210 Series
26
s I/O MAP
(Continued)
Address
Register
name
Access
Resource
name
Initial value
000000H *3
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXX
000001H *3
Port 1 data register
PDR1
R/W
Port 1
XXXXXXXX
000002H *3
Port 2 data register
PDR2
R/W
Port 2
XXXXXXXX
000003H *3
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXX
000004H *3
Port 4 data register
PDR4
R/W
Port 4
XXXXXXXX
000005H *3
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXX
000006H
Port 6 data register
PDR6
R/W
Port 6
1 1111111
000007H
Port 7 data register
PDR7
R/W
Port 7
– – XXXXXX
000008H
Port 8 data register
PDR8
R/W
Port 8
– – – – – XX X
000009H
to 0FH
(Reserved area) *1
000010H *3
Port 0 data direction register
DDR0
R/W
Port 0
0 0000000
000011H *3
Port1 data direction register
DDR1
R/W
Port 1
0 0000000
000012H *3
Port 2 data direction register
DDR2
R/W
Port 2
0 0000000
000013H *3
Port 3 data direction register
DDR3
R/W
Port 3
0 0000000
000014H *3
Port 4 data direction register
DDR4
R/W
Port 4
0 0000000
000015H *3
Port 5 data direction register
DDR5
R/W
Port 5
0 0000000
000016H
Analog input enable register
ADER
R/W
Port 6
1 1111111
000017H
Port 7 data direction register
DDR7
R/W
Port 7
– – 0 0 0 0 0 0
000018H
Port 8 data direction register
DDR8
R/W
Port 8
– – – – – 0 0 0
000019H
to 1FH
(Reserved area) *1
000020H
Mode control register 0
UMC0
R/W
UART (ch.0)
0 0000100
000021H
Status register 0
USR0
R/W
0 0010000
000022H
Input data register 0/output data
register 0
UIDR0/
UODR0
R/W
XXXXXXXX
000023H
Rate and data register 0
URD0
R/W
0 0000000
000024H
Mode control register 1
UMC1
R/W
UART (ch.1)
0 0000100
000025H
Status register 1
USR1
R/W
0 0010000
000026H
Input data register 1/output data
register 1
UIDR1/
UODR1
R/W
XXXXXXXX
000027H
Rate and data register 1
URD1
R/W
0 0000000