MB90210 Series
90
Table 20
Branch 1 [31 Instructions]
Note: For (a), (c) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: Set to 3 when branch is executed, and 2 when branch is not executed.
*2: 3
× (c) + (b)
*3: Reads (word) of the branch destination address.
*4: W pushes to stack (word), and R reads (word) of the branch destination address.
*5: Pushes to stack (word).
*6: W pushes to stack (long), and R reads (long) of the branch destination address.
*7: Pushes to stack (long).
Mnemonic
#
~
B
Operation
LH AH
IS
T
N
Z
V C RMW
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
JMP
@
A
JMP
addr16
JMP
@ear
JMP
@eam
JMPP
@ear *3
JMPP
@eam *3
JMPP
addr24
CALL
@ear *4
CALL
@eam *4
CALL
addr16 *5
CALLV
#vct4 *5
CALLP
@ear *6
CALLP
@eam *6
CALLP
addr24 *7
2
1
3
2
2 +
2
2 +
4
2
2 +
3
1
2
2 +
4
*1
2
3
4 + (a)
3
4 + (a)
3
4
5 + (a)
5
7
8 + (a)
7
0
(c)
0
(d)
0
(c)
2
× (c)
(c)
2
× (c)
2
× (c)
*2
2
× (c)
Branch if (Z) = 1
Branch if (Z) = 0
Branch if (C) = 1
Branch if (C) = 0
Branch if (N) = 1
Branch if (N) = 0
Branch if (V) = 1
Branch if (V) = 0
Branch if (T) = 1
Branch if (T) = 0
Branch if (V) xor (N) = 1
Branch if (V) xor (N) = 0
Branch if ((V) xor (N)) or (Z) = 1
Branch if ((V) xor (N)) or (Z) = 0
Branch if (C) or (Z) = 1
Branch if (C) or (Z) = 0
Branch unconditionally
word (PC)
← (A)
word (PC)
← addr16
word (PC)
← (ear)
word (PC)
← (eam)
word (PC)
← (ear), (PCB) ← (ear + 2)
word (PC)
← (eam), (PCB) ← (eam + 2)
word (PC)
← ad24 0 – 15,
(PCB)
← ad24 16 – 23
word (PC)
← (ear)
word (PC)
← (eam)
word (PC)
← addr16
Vector call instruction
word (PC)
← (ear) 0 – 15
(PCB)
← (ear) 16 – 23
word (PC)
← (eam) 0 – 15
(PCB)
← (eam) 16 – 23
word (PC)
← addr0 – 15,
(PCB)
← addr16 – 23
–